[PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it

[Mostafa Saleh]

On Mon, Jul 06, 2026 at 01:26:37PM -0300, Jason Gunthorpe wrote:
> [ This is part of the patch pile to move SMMUv3 over to the generic page
> table, the precursor patches have been merged now:
> 1) Organize the SMMUv3 invalidation flow so iommupt can use it
> 2) Use the generic iommu page table for SMMUv3
> 
> The whole branch is here:
>    https://github.com/jgunthorpe/linux/commits/iommu_pt_arm64/
> ]
> 
> iommupt has a design that focuses on building a single iommu_iotlb_gather
> for arbitary batches of map/unmap operations. The gather uses the free
> list and it captures invalidations of tables, leaves and supports mixed
> levels.
> 
> The introduction of PT_FEAT_DETAILED_GATHER provides some additional
> information that is useful for ARM: the damage bitmaps for the table and
> level changes.
> 
> Prior to switching SMMUv3 over to use iommupt prepare for this by
> reworking the internal invalidation to work on the same data format that
> iommupt will produce. Bridge the invalidations generated by io-pgtable
> into the new format. The conversion is simple enough, io-pgtable generates
> invalidation operations that have only a single set bit in
> table_levels_bitmap/leaf_levels_bitmap, so we can convert the io-pgtable
> provided size into the proper level leaf or table bit.
> 
> When iommupt uses this mechanism it will fill in full bitmaps reflecting
> the union of all invalidations contained in the gather, and this series
> provides an implementation that can work this way.
> 
> Like the other drivers the general algorithm focuses on trying to issue a
> single command per gather or at most 512 single invalidations. If that
> isn't possible then it falls back to full invalidation. Since table and
> leaf invalidation are combined together there is no waste of invaliding
> tables prior to performing a full invalidation.
> 
> On its own this provides value as the invalidation has a number of
> rough spots:
> 
>  - Non-leaf invalidation actually expands into a TLBI for every
>    translation granule because the inner logic doesn't special case the
>    walk vs leaf condition. Now that a table_levels_bitmap is used to
>    describe the walk invalidation it properly generates a RIL with optimal
>    TTL or only one single invalidation.
> 
>  - RIL doesn't calculate perfect hints for SVA because the SVA rules are
>    different from the io-pgtable-arm rules that the RIL algorithm works
>    with. SVA can now express the combined leaf and table invalidation that
>    the MM callback represents and get the right TTL, with an optimization
>    for the common 4k only scenario.
> 
>  - RIL didn't generate a single invalidation like VT-d and AMD do,
>    instead it tries to generate an exact coverage with many
>    smaller invalidations. Switch it to match the other drivers single
>    range approach for performance and consistency. Since ARM has a much
>    more flexible range definition the over invalidation is far smaller
>    than other systems.
> 
> The approach is to introduce a new struct arm_smmu_tlbi which
> describes the invalidation, pre-compute into the tlbi the single and
> range commands from the start/last and bitmaps, and then apply the
> correct pre-computed command to each of items in the invalidation
> list.
> 
> The RIL and single calculations are revised to use the new bitmaps
> and accurately generate TTL/stride/etc.
> 
> Some of this design is to support another series to remove the batch on
> the stack. Now that we have the invalidation list and the tlbi it is
> simple to just expand the invs list directly into commands instead of
> using the temporary on-stack batch array. Eventually removing batch will
> save ~1k of stack usage here.
> 
> v2:
>  - Rebase to v7.2-rc1
> v1: https://lore.kernel.org/all/0-v1-5b1ac97a5403+6588f-smmu_tlbi_jgg@nvidia.com/
> 
> Jason Gunthorpe (8):
>   iommu/arm-smmu-v3: Pass the parameters for the invalidation in a
>     struct
>   iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv
>   iommu/arm-smmu-v3: Optimize range invalidation for latency
>   iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used
>   iommu/arm-smmu-v3: Precompute the invalidation commands
>   iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain
>   iommu/arm-smmu-v3: Change how the tlbi describes the invalidation
>   iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE

I quickly went through the series, and left few comments.
As discussed before regarding the TLB invalidation logic sharing
with pKVM [1], I still think after these changes both drivers can
share some logic on the level arm_smmu_tlbi_calc_range() (+ tweaks).
I am planning to post my series by this week, I will keep it based
on upstream and I can rework my series later if this one gets merged
first.

Thanks,
Mostafa

[1] https://lore.kernel.org/all/20260501111928.259252-5-smostafa@google.com/

> 
>  .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c   |  32 +-
>  .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c  |  30 +-
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c   | 439 ++++++++++++------
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h   |  54 ++-
>  4 files changed, 382 insertions(+), 173 deletions(-)
> 
> 
> base-commit: 4c73a6222c248384513c4f465e547df80b280a06
> -- 
> 2.43.0
>