[PATCH 2/9] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness

[Cristian Ciocaltea]

Hi Diederik,

On 7/5/26 4:28 PM, Diederik de Haas wrote:
> Hi Cristian,
> 
> On Wed Jun 17, 2026 at 8:52 PM CEST, Cristian Ciocaltea wrote:
>> Assert the AXI reset in the CRTC disable path, and the VP DCLK reset in
>> the enable path.
>>
>> These resets are intended to leave the hardware in a clean state for the
>> next use, helping recover from exceptions such as IOMMU page faults, as
>> well as to prevent random display output glitches, such as a blank
>> image, observed when switching modes that also change the color format,
>> e.g. from RGB to YUV420 and vice versa.
>>
>> For now this seems to affect only the RK3588, hence the resets are
>> optional and will be provided in the device tree for this SoC only.
> 
> Why do you think it only effect RK3588? 

My findings are exclusively in the context of validating YUV support for DW HDMI
QP, hence targeting RK3588 and RK3576.  Since RK3576 didn't exhibit any
anomalies, I concluded the resets are needed just for RK3588.

> I reported about my RK3568 test here:
> https://lore.kernel.org/linux-rockchip/DFRU6ODDM71P.3NQGLRK8IVDUY@cknow-tech.com/
> "I then went on to try LibreELEC's builds. The artifacts I (sometimes)
> saw, were gone :-D OTOH, I did get several major issues 'in return',
> like rk_iommu Page fault resulting in a black screen and the only way to
> 'recover' from it, was a reboot."
> 
> And I reported some more test results here:
> https://forum.libreelec.tv/thread/29953-le13-testing-for-rk3288-rk3328-rk3399-rk3566-rk3568-rk3576-rk3588/?postID=204691#post204691
> 
> That seems to me a (strong) indication it also affects RK3566/RK3568?

If coincidentally this helps improve the reliability of some of the older SoCs
as well, the resets can easily be added to the corresponding DTs and submitted
as a follow-up series.

Cristian