[PATCH] dt-bindings: iio: adc: convert Xilinx XADC bindings to YAML
Avermoal
avermoal at gmail.com
Sun Jul 5 01:53:08 PDT 2026
Convert the Xilinx XADC binding documentation from .txt to YAML format.
This conversion is part of the ongoing effort to migrate all DT bindings
to a machine-verifiable schema.
The new xilinx-xadc.yaml file was created from the original .txt and
includes all necessary properties, descriptions, and examples. The
conversion also fixes a minor typo in the 'xlnx,channels' property name.
Signed-off-by: Avermoal <avermoal at gmail.com>
---
.../bindings/iio/adc/xilinx-xadc.txt | 141 -------------
.../bindings/iio/adc/xilinx-xadc.yaml | 186 ++++++++++++++++++
2 files changed, 186 insertions(+), 141 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
- - compatible: Should be one of
- * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
- configuration interface to interface to the XADC hardmacro.
- * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
- interface to the XADC hardmacro.
- * "xlnx,system-management-wiz-1.3": When using the
- Xilinx System Management Wizard fabric IP core to access the
- UltraScale and UltraScale+ System Monitor.
- - reg: Address and length of the register set for the device
- - interrupts: Interrupt for the XADC control interface.
- - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
- when using the axi-xadc or the axi-system-management-wizard this must be
- the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
- - xlnx,external-mux:
- * "none": No external multiplexer is used, this is the default
- if the property is omitted.
- * "single": External multiplexer mode is used with one
- multiplexer.
- * "dual": External multiplexer mode is used with two
- multiplexers for simultaneous sampling.
- - xlnx,external-mux-channel: Configures which pair of pins is used to
- sample data in external mux mode.
- Valid values for single external multiplexer mode are:
- 0: VP/VN
- 1: VAUXP[0]/VAUXN[0]
- 2: VAUXP[1]/VAUXN[1]
- ...
- 16: VAUXP[15]/VAUXN[15]
- Valid values for dual external multiplexer mode are:
- 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
- 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
- ...
- 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
- This property needs to be present if the device is configured for
- external multiplexer mode (either single or dual). If the device is
- not using external multiplexer mode the property is ignored.
- - xnlx,channels: List of external channels that are connected to the ADC
- Required properties:
- * #address-cells: Should be 1.
- * #size-cells: Should be 0.
-
- The child nodes of this node represent the external channels which are
- connected to the ADC. If the property is no present no external
- channels will be assumed to be connected.
-
- Each child node represents one channel and has the following
- properties:
- Required properties:
- * reg: Pair of pins the channel is connected to.
- 0: VP/VN
- 1: VAUXP[0]/VAUXN[0]
- 2: VAUXP[1]/VAUXN[1]
- ...
- 16: VAUXP[15]/VAUXN[15]
- Note each channel number should only be used at most
- once.
- Optional properties:
- * xlnx,bipolar: If set the channel is used in bipolar
- mode.
-
-
-Examples:
- xadc at f8007100 {
- compatible = "xlnx,zynq-xadc-1.00.a";
- reg = <0xf8007100 0x20>;
- interrupts = <0 7 4>;
- interrupt-parent = <&gic>;
- clocks = <&pcap_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel at 0 {
- reg = <0>;
- };
- channel at 1 {
- reg = <1>;
- };
- channel at 8 {
- reg = <8>;
- };
- };
- };
-
- xadc at 43200000 {
- compatible = "xlnx,axi-xadc-1.00.a";
- reg = <0x43200000 0x1000>;
- interrupts = <0 53 4>;
- interrupt-parent = <&gic>;
- clocks = <&fpga1_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel at 0 {
- reg = <0>;
- xlnx,bipolar;
- };
- };
- };
-
- adc at 80000000 {
- compatible = "xlnx,system-management-wiz-1.3";
- reg = <0x80000000 0x1000>;
- interrupts = <0 81 4>;
- interrupt-parent = <&gic>;
- clocks = <&fpga1_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel at 0 {
- reg = <0>;
- xlnx,bipolar;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml
new file mode 100644
index 000000000000..d61635516ce2
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.yaml
@@ -0,0 +1,186 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xilinx-xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx 7 Series XADC and UltraScale/UltraScale+ System Monitor
+
+maintainers:
+ - Avermoal <avermoal at gmail.com>
+
+description: |
+ The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
+ The XADC has a DRP interface for communication. Currently two different
+ frontends for the DRP interface exist. One that is only available on the ZYNQ
+ family as a hardmacro in the SoC portion of the ZYNQ. The other one is
+ available on all series 7 platforms and is a softmacro with an AXI interface.
+ This binding document describes the bindings for both of them since the
+ bindings are very similar.
+
+ The Xilinx System Monitor is an ADC that is found in the UltraScale and
+ UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface
+ for communication. Xilinx provides a standard IP core that can be used to
+ access the System Monitor through an AXI interface in the FPGA fabric.
+ This IP core is called the Xilinx System Management Wizard. This document
+ describes the bindings for this IP.
+
+properties:
+ compatible:
+ description: |
+ Specifies the interface type and the target device.
+ - "xlnx,zynq-xadc-1.00.a"
+ for ZYNQ device configuration interface (hardmacro in SoC)
+ - "xlnx,axi-xadc-1.00.a"
+ for AXI pcore softmacro on all Series 7 FPGAs
+ - "xlnx,system-management-wiz-1.3"
+ for UltraScale/UltraScale+ System Monitor via AXI
+ enum:
+ - xlnx,zynq-xadc-1.00.a
+ - xlnx,axi-xadc-1.00.a
+ - xlnx,system-management-wiz-1.3
+
+ reg:
+ description: Address and length of the register set for the device.
+ maxItems: 1
+
+ interrupts:
+ description: Interrupt for the XADC control interface.
+ maxItems: 1
+
+ clocks:
+ description: |
+ When using the ZYNQ this must be the ZYNQ PCAP clock,
+ when using the axi-xadc or the axi-system-management-wizard this must be
+ the clock that provides the clock to the AXI bus interface of the core.
+ maxItems: 1
+
+ xlnx,external-mux:
+ description: |
+ External multiplexer mode. If omitted, defaults to "none".
+ - "none" – no external multiplexer (default)
+ - "single" – one external multiplexer
+ - "dual" – two external multiplexers for simultaneous sampling
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [none, single, dual]
+ default: none
+
+ xlnx,external-mux-channel:
+ description: |
+ Configures which pair of pins is used to sample data in external mux mode.
+ For single mode: 0 (VP/VN) or 1..16 (VAUXP[0..15]/VAUXN[0..15]).
+ For dual mode: 1..8, where the value n corresponds to the pair
+ (VAUXP[n-1]/VAUXN[n-1] and VAUXP[n+7]/VAUXN[n+7]).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 16
+
+ xlnx,channels:
+ description: |
+ Container for external channels that are connected to the ADC.
+ If this property is not present, no external channels will be assumed.
+ type: object
+ properties:
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 0
+ patternProperties:
+ "^channel@[0-9a-f]+$":
+ type: object
+ description: Each child node represents one external channel.
+ properties:
+ reg:
+ description: |
+ Pair of pins the channel is connected to.
+ 0: VP/VN
+ 1..16: VAUXP[0..15]/VAUXN[0..15]
+ maxItems: 1
+ xlnx,bipolar:
+ description: If present, the channel is used in bipolar mode.
+ type: boolean
+ required:
+ - reg
+ additionalProperties: false
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ additionalProperties: false
+
+allOf:
+ - if:
+ required:
+ - xlnx,external-mux
+ properties:
+ xlnx,external-mux:
+ enum: [single, dual]
+ then:
+ required:
+ - xlnx,external-mux-channel
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ xadc at f8007100 {
+ compatible = "xlnx,zynq-xadc-1.00.a";
+ reg = <0xf8007100 0x20>;
+ interrupts = <0 7 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&pcap_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel at 0 {
+ reg = <0>;
+ };
+ channel at 1 {
+ reg = <1>;
+ };
+ channel at 8 {
+ reg = <8>;
+ };
+ };
+ };
+ - |
+ xadc at 43200000 {
+ compatible = "xlnx,axi-xadc-1.00.a";
+ reg = <0x43200000 0x1000>;
+ interrupts = <0 53 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel at 0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
+ - |
+ adc at 80000000 {
+ compatible = "xlnx,system-management-wiz-1.3";
+ reg = <0x80000000 0x1000>;
+ interrupts = <0 81 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel at 0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
+...
--
Changes in v2:
- Fix conditional requirement for xlnx,external-mux-channel (add if/required block)
- Correct reg type in child nodes (use maxItems: 1 instead of items)
- Make #address-cells and #size-cells required under xlnx,channels
2.52.0
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