[PATCH 7/8] arm64: dts: qcom: eliza: Add GPU nodes
Akhil P Oommen
akhilpo at oss.qualcomm.com
Sun Jul 5 01:14:22 PDT 2026
From: Puranam V G Tejaswi <puranam.tejaswi at oss.qualcomm.com>
Adreno 722 found in Eliza chipset belongs to the A7x GEN1 family. It is
derived from A730 and shares the same IP-level configurations: HWCG
registers, protected registers, GBIF CX registers and gmu_cgc_mode.
Major differences include lower cache/core counts, 1MB GMEM, no
Concurrent Binning & LPAC support. Some of the peripheral blocks like
RSCC are from A740 that resulted in updates to RSC layout.
Add the necessary devicetree nodes to describe this GPU.
Signed-off-by: Puranam V G Tejaswi <puranam.tejaswi at oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo at oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 152 ++++++++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index e5b8377e6c3a..c24c5e9695d5 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -3742,6 +3742,158 @@ nsp_noc: interconnect at 320c0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
+
+ gpu: gpu at 3d00000 {
+ compatible = "qcom,adreno-43020100", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0x0 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&gpu_micro_code_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2-adreno",
+ "operating-points-v2";
+
+ opp-259000000 {
+ opp-hz = /bits/ 64 <259000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <781250>;
+ qcom,opp-acd-level = <0xc82f5ffd>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <2136718>;
+ qcom,opp-acd-level = <0xc82f5ffd>;
+ };
+
+ opp-515000000 {
+ opp-hz = /bits/ 64 <515000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <5285156>;
+ qcom,opp-acd-level = <0xc02d5ffd>;
+ };
+
+ opp-645000000 {
+ opp-hz = /bits/ 64 <645000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <6074218>;
+ qcom,opp-acd-level = <0x882f5ffd>;
+ };
+
+ opp-724000000 {
+ opp-hz = /bits/ 64 <724000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <6671875>;
+ qcom,opp-acd-level = <0xa82d5ffd>;
+ };
+
+ opp-796000000 {
+ opp-hz = /bits/ 64 <796000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <10687500>;
+ qcom,opp-acd-level = <0x882d5ffd>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <10687500>;
+ qcom,opp-acd-level = <0x882d5ffd>;
+ };
+
+ opp-975000000 {
+ opp-hz = /bits/ 64 <975000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <12449218>;
+ qcom,opp-acd-level = <0x882c5ffd>;
+ };
+
+ opp-1075000000 {
+ opp-hz = /bits/ 64 <1075000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ };
+
+ opp-1150000000 {
+ opp-hz = /bits/ 64 <1150000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa8295ffd>;
+ };
+ };
+ };
+
+ gmu: gmu at 3d6a000 {
+ compatible = "qcom,adreno-gmu-722.0", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x35000>,
+ <0x0 0x03d50000 0x0 0x10000>,
+ <0x0 0x0b290000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_DEMET_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "hub",
+ "demet";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 0x5 0x0>;
+ qcom,qmp = <&aoss_qmp>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-220000000 {
+ opp-hz = /bits/ 64 <220000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+ };
};
thermal-zones {
--
2.54.0
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