[PATCH v3 00/40] KVM: arm64: Add GICv5 IRS support
Sascha Bischoff
Sascha.Bischoff at arm.com
Fri Jul 3 08:50:32 PDT 2026
Hi all,
This series builds on the initial vGICv5 support [1] and adds support
for the GICv5 IRS, as described by the GICv5 (EAC0) specification [2].
With this, a GICv5 guest is no longer restricted to PPIs, and can make
use of SPIs and LPIs as well.
With SPIs and LPIs available, this series makes it possible to boot a
full Linux guest on the Arm FVP model [3], using the setup described
in Lorenzo's GICv5 Linux software enablement guide [4]. In addition,
GICv5 IPIs are typically implemented as LPIs, so LPI support is what
makes guests with more than one vCPU possible.
The corresponding kvmtool changes are available separately [5]. With
these changes, `--irqchip=gicv5` works now. The `--irqchip=gicv5-its`
configuration does not work with this series, as ITS/MSI support is
not included here.
The IRS is created as part of the vgic-v5 device, and is not a
separate KVM device. This is because implementing the CPU interface
alone would limit a guest to a single vCPU and PPIs only. Hence, the
IRS is bundled into the VGIC, much like the distributor for GICv3.
The series adds the host-side plumbing needed for KVM to interact with
the physical IRS, including VM and VPE table management, VPE
residency, and VPE doorbells. It also adds an emulated IRS MMIO
interface for the guest, together with the UAPI needed for userspace
to configure the IRS address and to save/restore the IRS and IST
state.
The main pieces are:
* Host IRS capability discovery and configuration frame plumbing.
* Allocation and management of the GICv5 VM table, VPE table, VMTEs,
VPEs, and guest IST backing storage.
* VPE residency and doorbell handling, allowing the IRS to select SPIs
and LPIs for resident VPEs and wake non-resident VPEs when required.
* Emulation of the GICv5 IRS MMIO CONFIG_FRAME for guests.
Virtualisation, MPAM, MEC, SWERR are not supported and are RAZ/WI.
* SPI injection support using GIC VDPEND, together with tracking of
in-flight SPIs so that deactivation notifiers can still be handled.
* Save/restore support for GICv5 EL1 system registers, IRS MMIO state,
and guest ISTs.
* Documentation for the new VGICv5 IRS userspace interfaces and the
required save/restore ordering.
Please pay close attention to the save/restore interface and ordering,
in particular to make sure that no guest state has been omitted.
LPIs are explicitly driven by the guest through the IRS/IST state. This
series does not add direct LPI injection support, and does not add MSI
support. It also does not add GICv5 ITS emulation.
These changes are based on v7.2-rc1. I've pushed the full set of changes
to a branch at [6].
Changes since v2 [8]:
* Added emulation for the IRS CoreSight identification registers.
* Tightened ACPI GICv5 KVM setup, including maintenance IRQ handling
and cleanup on setup failures.
* Hardened VM/VPE table handling, including invalid VM ID checks,
vcpu_idx based VPE IDs, and less noisy error paths.
* Accounted guest IST backing allocations with GFP_KERNEL_ACCOUNT.
* Made VMTE/VMT teardown paths avoid reusing state that could not be
safely invalidated or released.
* Improved IST save/restore memory accesses by adding SRCU protection
for LPI IST save.
Thanks for taking the time to look at these changes. Apologies for the
size of the series, but this is a rather hard set to disentangle and
review separately!
Thanks,
Sascha
[1] https://lore.kernel.org/all/20260319154937.3619520-1-sascha.bischoff@arm.com/
[2] https://developer.arm.com/documentation/aes0070/latest
[3] https://developer.arm.com/documentation/108086/latest
[4] https://linaro.atlassian.net/wiki/x/CQAF-wY
[5] https://lore.kernel.org/all/20260116182606.61856-1-sascha.bischoff@arm.com/
[6] https://gitlab.arm.com/linux-arm/linux-sb/-/tree/gicv5_kvm_irs_support_v3
[7] https://lore.kernel.org/all/20260427160547.3129448-1-sascha.bischoff@arm.com/
[8] https://lore.kernel.org/all/20260521144846.1899475-1-sascha.bischoff@arm.com/
Sascha Bischoff (40):
irqchip/gic-v5: Allow KVM setup without a maintenance IRQ
irqchip/gic-v5: Provide OF IRS config frame attrs to KVM
irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts
KVM: arm64: gic-v5: Define remaining IRS MMIO registers
arm64/sysreg: Add GICv5 GIC VDPEND and VDRCFG encodings
arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields
KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame
KVM: arm64: gic-v5: Add VPE doorbell domain
KVM: arm64: gic-v5: Create and manage VM and VPE tables
KVM: arm64: gic-v5: Introduce guest IST alloc and management
KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops
KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific
KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops
KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells
KVM: arm64: gic-v5: Add resident/non-resident hyp calls
KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI
KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address
KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers
KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI
KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation
KVM: arm64: gic-v5: Initialise per-VM IRS state
KVM: arm64: gic-v5: Register the IRS IODEV
KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state
KVM: arm64: selftests: Update vGICv5 selftest to set IRS address
KVM: arm64: gic-v5: Introduce SPI AP list
KVM: arm64: gic-v5: Add GIC VDPEND and GIC VDRCFG hyp calls
KVM: arm64: gic-v5: Track SPI state for in-flight SPIs
KVM: arm64: gic: Introduce set_pending_state() to irq_op
KVM: arm64: gic-v5: Support SPI injection
Documentation: KVM: Extend VGICv5 docs for KVM_VGIC_V5_ADDR_TYPE_IRS
KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd
KVM: arm64: gic-v5: Mask per-vcpu PPI state in
vgic_v5_finalize_ppi_state()
KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors
KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region
KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS
KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs
Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for
VGICv5
Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs
Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST
Documentation: KVM: Add the VGICv5 IRS save/restore sequences
.../virt/kvm/devices/arm-vgic-v5.rst | 237 ++-
arch/arm64/include/asm/kvm_asm.h | 4 +
arch/arm64/include/asm/kvm_hyp.h | 4 +
arch/arm64/include/asm/sysreg.h | 18 +-
arch/arm64/include/uapi/asm/kvm.h | 7 +
arch/arm64/kvm/Makefile | 3 +-
arch/arm64/kvm/arm.c | 2 +-
arch/arm64/kvm/hyp/nvhe/hyp-main.c | 34 +
arch/arm64/kvm/hyp/vgic-v5-sr.c | 55 +
arch/arm64/kvm/sys_regs.c | 6 +-
arch/arm64/kvm/vgic-sys-reg-v5.c | 519 +++++
arch/arm64/kvm/vgic/vgic-init.c | 111 +-
arch/arm64/kvm/vgic/vgic-irqfd.c | 17 +-
arch/arm64/kvm/vgic/vgic-irs-v5.c | 1138 ++++++++++
arch/arm64/kvm/vgic/vgic-kvm-device.c | 252 ++-
arch/arm64/kvm/vgic/vgic-mmio.c | 6 +
arch/arm64/kvm/vgic/vgic-mmio.h | 2 +
arch/arm64/kvm/vgic/vgic-v5-tables.c | 1855 +++++++++++++++++
arch/arm64/kvm/vgic/vgic-v5-tables.h | 112 +
arch/arm64/kvm/vgic/vgic-v5.c | 1220 ++++++++++-
arch/arm64/kvm/vgic/vgic.c | 39 +-
arch/arm64/kvm/vgic/vgic.h | 21 +-
arch/arm64/tools/sysreg | 4 +-
drivers/irqchip/irq-gic-v5-irs.c | 19 +-
drivers/irqchip/irq-gic-v5.c | 117 +-
include/kvm/arm_vgic.h | 165 +-
include/linux/irqchip/arm-gic-v5.h | 256 ++-
include/linux/irqchip/arm-vgic-info.h | 5 +
tools/arch/arm64/include/uapi/asm/kvm.h | 7 +
tools/testing/selftests/kvm/arm64/vgic_v5.c | 6 +
.../selftests/kvm/include/arm64/gic_v5.h | 3 +
31 files changed, 6093 insertions(+), 151 deletions(-)
create mode 100644 arch/arm64/kvm/vgic-sys-reg-v5.c
create mode 100644 arch/arm64/kvm/vgic/vgic-irs-v5.c
create mode 100644 arch/arm64/kvm/vgic/vgic-v5-tables.c
create mode 100644 arch/arm64/kvm/vgic/vgic-v5-tables.h
--
2.34.1
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