[PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings

[Frank Li]

On Thu, Jul 02, 2026 at 10:35:00AM +0300, Ioana Ciornei wrote:
> On Wed, Jul 01, 2026 at 09:27:03AM -0500, Frank Li wrote:
> > On Wed, Jul 01, 2026 at 04:11:33PM +0300, Ioana Ciornei wrote:
> > > From: Vladimir Oltean <vladimir.oltean at nxp.com>
> > >
> > > Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
> > > instance is present in the compatible string, to allow reliable per-lane
> > > capability detection and per-lane customization of electrical properties.
> > >
> > > The modern bindings are backward-incompatible with old kernels, due
> > > to the consumer phandles being either in one form or in another, as
> > > explained here:
> > > https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
> > >
> > > One of the major differences between the LX2160A and LX2162A is the
> > > SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
> > > split that up even further, and derive a fsl-lx2162a.dtsi which
> > > overrides the SerDes properties.
> > >
> > > Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
> > > Signed-off-by: Ioana Ciornei <ioana.ciornei at nxp.com>
> > > ---
> > > Changes in v2:
> > > - Enable serdes_1 on all board DTs that has consumers for it.
> > > - Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
> > > - Remove paragraph from commit message which mentioned some consumer
> > > changes that are no longer needed nor part of the commit.
> > > ---
> > >  .../freescale/fsl-lx2160a-clearfog-itx.dtsi   |   4 +
> > >  .../dts/freescale/fsl-lx2160a-half-twins.dts  |   4 +
> > >  .../boot/dts/freescale/fsl-lx2160a-rdb.dts    |   4 +
> > >  .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
> > >  .../dts/freescale/fsl-lx2162a-clearfog.dts    |   6 +-
> > >  .../boot/dts/freescale/fsl-lx2162a-qds.dts    |   2 +-
> > >  .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi |  24 +++
> > >  7 files changed, 190 insertions(+), 4 deletions(-)
> > >  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> > >
> > ...
> > >
> > > +&serdes_1 {
> > > +       status = "okay";
> > > +};
> > > +
> >
> > Can you try keep alphabet order? may old file is not ordersed, but try
> > best, at least should before &uart0
>
> Sure, will move it.
>
> >
> > >  &uart1 {
> > >         status = "okay";
> > >  };
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > index 1d73abffa6b7..a687eb3e3190 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > Please split chips dtsi and boards dts to two patch.
>
> Ok, I will split the serdes_1 explicit enable into a prep patch.
>
> >
> > > @@ -621,17 +621,163 @@ soc: soc {
> > >                 ranges;
> > >                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> > >
> > > +               /* Note on the interpretation of SerDes lane numbering from
> > > +                * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
> > > +                * The letters (A-H) correspond to logical lane numbers in the
> > > +                * SerDes register map (lane A's registers start with LNAGCR0),
> > > +                * while the numbers (0-7) correspond to physical lanes as
> > > +                * routed to pins.  SerDes block #1 is flipped in the LX2160A
> > > +                * floorplan (logical lane A goes to physical lane 7's pins),
> > > +                * while SerDes blocks #2 and #3 are not.  The lanes below are
> > > +                * listed right to left when looking at that table.
> > > +                * Both the numbers and the letters are according to the logical
> > > +                * numbering scheme, and do not account for the flipping.
> > > +                */
> > ...
> > > +                       compatible = "fsl,lx2160a-serdes3";
> > > +                       reg = <0x0 0x1ec0000 0x0 0x1e30>;
> > > +                       #address-cells = <1>;
> > > +                       #size-cells = <0>;
> > > +                       status = "disabled";
> >
> > status should be last property
>
> Ok, will move it.
>
> >
> > > +                       #phy-cells = <1>;
> > > +
> > > +                       serdes_3_lane_a: phy at 0 {
> > > +                               reg = <0>;
> > > +                               #phy-cells = <0>;
> > > +                       };
> > > +
> > ...
> > > +
> > > +#include "fsl-lx2160a-rev2.dtsi"
> > > +
> > > +&serdes_1 {
> > > +       compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
> > > +
> > > +       /delete-node/ phy at 0;
> > > +       /delete-node/ phy at 1;
> > > +       /delete-node/ phy at 2;
> > > +       /delete-node/ phy at 3;
> >
> > Now, do not perfer delete-node. if ver2 is not include phy at 0, ...
> >
> > create ver2 files, let ver2 include it. Now most people like A + B, not
> > A - B.
> >
>
> I am not sure I follow what you say about the ver2 files - are you
> referring to -rev2 or LX2162A?
>
> The LX2162A is a version of the LX2160A SoC, also known as "LX2-Lite".
> And the main difference is that the LX2162A does not have the 3rd SerDes
> block and only 4 SerDes lanes on the first block.

If it is the same die and it is disable by fuse box. I suggest leave it here
now because default it is disabled and try to access-control-cell in future.

https://lore.kernel.org/imx/20241212-imx-ocotp-v1-1-198bb0af86a0@nxp.com/

That these nodes can be dymatically disabled it.

If it is difference die, it should lx2160a.dtsi include lx2-lite. you
can rename old lx2160a.dtsi to lx2-lites.dtsi. You need adjust file name
and I just said overwhole method.

Frank

>
> The delete-node is reflecting exactly how the SoCs came about, the
> LX2162A is a smaller version of the LX2160A (which came first) and not
> the other way around.
>
> I feel like it's unnecessary churn but let me know if you feel strongly
> about this.
>
> Thanks,
> Ioana