[PATCH v4 0/8] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

[Diederik de Haas]

Hi Cristian,

On Fri Jun 12, 2026 at 1:46 AM CEST, Cristian Ciocaltea wrote:
> This series provides a set of bug fixes and cleanups for the Rockchip
> Samsung HDPTX PHY driver.
>
> The first part of the series addresses clock rate calculation and
> synchronization issues.  Specifically, it fixes edge cases where the PHY
> PLL is pre-programmed by an external component (like a bootloader) or
> when changing the color depth (bpc) while keeping the modeline constant.
> Because the Common Clock Framework .set_rate() callback might not be
> invoked if the pixel clock remains unchanged, this previously led to
> out-of-sync states between CCF and the actual HDMI PHY configuration.
>
> The second part focuses on code cleanups and modernizing the register
> access.  Now that dw_hdmi_qp driver has fully switched to using
> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> and the restrict_rate_change flag logic.  Finally, it refactors the
> driver to consistently use standard bitfield macros.

I built a 7.2-rc1 based kernel with this patch set and used that on my
NanoPC-T6 LTS connected to my 4K TV. The kernel also has the HDMI 2.0 patch
set, so I can get 4K at 60 with it. When I then tried to switch to 10bpc with
``modetest -M rockchip -w 86:'max bpc':10`` nothing happened.
But that's expected as my TV only supports HDMI 2.0 and not HDMI 2.1.

When I add ``video=HDMI-A-1:1920x1080 at 60`` to the kernel command line, then it
starts up with 10bpc and I can change to 8bpc and back to 10bpc.
So feel free to add my

Tested-by: Diederik de Haas <diederik at cknow-tech.com>  # NanoPC-T6 LTS

Cheers,
  Diederik

>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
> ---
> Changes in v4:
> - Added new patches to address new findings from Sashiko:
>   * Prevent divide-by-zero when computing clk rate
>   * Fix rate recalculation for 3.2GHz FRL
> - Updated patch "Consistently use bitfield macros" to handle a few more
>   bit operations
> - Link to v3: https://patch.msgid.link/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com
>
> Changes in v3:
> - Replaced div_u64() with DIV_ROUND_CLOSEST_ULL() in Patch 1 (Sashiko)
> - Fixed theoretical usage_count unbalanced issue in Patch 2 (Sashiko)
> - Rebased series onto latest phy/next
> - Link to v2: https://patch.msgid.link/20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com
>
> Changes in v2:
> - Collected Tested-by tags from Thomas and Simon
> - Fixed a typo in commit description of patch 1
> - Added a comment in patch 2 explaining why PLL config errors are
>   ignored for rk_hdptx_phy_consumer_get()
> - Added a missed FIELD_GET conversion for lcpll_hw.pms_sdiv in patch 6
> - Rebased onto latest phy/fixes
> - Link to v1: https://lore.kernel.org/r/20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com
>
> ---
> Cristian Ciocaltea (8):
>       phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
>       phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate
>       phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL
>       phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
>       phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
>       phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
>       phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
>       phy: rockchip: samsung-hdptx: Consistently use bitfield macros
>
>  drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 266 +++++++++++-----------
>  1 file changed, 130 insertions(+), 136 deletions(-)
> ---
> base-commit: 293e19f416fa3f233a2fb013258f7abcb39ad6ed
> change-id: 20260227-hdptx-clk-fixes-47426632f862
>
>
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