[PATCH v4 1/4] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio

Yu-Chun Lin [林祐君] eleanor.lin at realtek.com
Wed Jul 1 03:31:28 PDT 2026


Hi Linus,

> Hi Yu-Chun,
> 
> thanks for your patch!
> 
> On Mon, Jun 22, 2026 at 10:33 AM Yu-Chun Lin <eleanor.lin at realtek.com>
> wrote:
> 
> > From: Tzuyi Chang <tychang at realtek.com>
> >
> > Add the device tree bindings for the Realtek DHC (Digital Home Center)
> > RTD1625 GPIO controllers.
> >
> > The RTD1625 GPIO controller features a per-pin register architecture
> > that differs significantly from previous generations. It utilizes
> > separate register blocks for GPIO configuration and interrupt control.
> >
> > Reviewed-by: Krzysztof Kozlowski
> > <krzysztof.kozlowski at oss.qualcomm.com>
> > Signed-off-by: Tzuyi Chang <tychang at realtek.com>
> > Signed-off-by: Yu-Chun Lin <eleanor.lin at realtek.com>
> (...)
> 
> > +  interrupt-controller: true
> > +
> > +  "#interrupt-cells":
> > +    const: 2
> > +
> > +  gpio-ranges: true
> > +
> > +  gpio-controller: true
> > +
> > +  "#gpio-cells":
> > +    const: 2
> 
> After looking at the driver I must challenge this binding.
> 
> Your driver is full of (offset % 32) and even (offset % 32) *4 to just work around
> the fact that the hardware inherently has 32-pin banks.
> 
> Instead of using twocell GPIO and irqs, just use threecell, interrupt-cells and
> gpio-cells 3.
> 
> First cell is bank, second cell is offset inside each bank.
> 
> For Linux specifically there are helpers for dealing with this in gpiolib, and
> further you will be able to use the GPIO_GENERIC library, while this is beside
> the point for the binding itself.
> 
> Yours,
> Linus Walleij

To clarify the hardware design: this SoC does not use a banked GPIO
architecture.

Each GPIO pin has its own dedicated 32-bit control register that handles
both GPIO configuration and interrupt settings (e.g., edge/level enable).
The only exception is the interrupt status register, which is grouped into
32-bit words.

Since physical GPIO banks do not exist, using a 3-cell <bank offset flags>
format would misrepresent the hardware. Therefore,
keeping #gpio-cells = <2> and #interrupt-cells = <2> is the most accurate
reflection of the actual silicon.

Best Regards,
Yu-Chun


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