On 26-01-13 15:52:42, Marco Felsch wrote: > Some parallel panels have a pixelclk of 24.19 MHz. Add support for > 241.90 MHz so a by 10 divider can be used to derive the exact pixelclk. > > Signed-off-by: Marco Felsch <m.felsch at pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa at oss.qualcomm.com>