[PATCH] i2c: xiic: add ACPI support

[Abdurrahman Hussain]

> On Jan 15, 2026, at 11:30 PM, Michal Simek <michal.simek at amd.com> wrote:
> 
> 
> 
> On 1/15/26 20:04, Abdurrahman Hussain wrote:
>>> On Jan 15, 2026, at 5:02 AM, Wolfram Sang <wsa+renesas at sang-engineering.com> wrote:
>>> 
>>> On Thu, Jan 15, 2026 at 12:28:46AM +0000, Abdurrahman Hussain wrote:
>>>> Use generic device property accessors.
>>>> Make the clock optional assuming it's managed by firmware.
>>>> 
>>>> Signed-off-by: Abdurrahman Hussain <abdurrahman at nexthop.ai>
>>> 
>>> On which hardware has this been tested?
>>> 
>> This was tested on nexthop.ai data-center NH-4010 switch with Xilinx based FPGA.
>> The following ACPI ASL fragment was used to describe the device:
>>             Device (I2C2) {
>>                 Name (_HID, "PRP0001")
>>                 Name (_CRS, ResourceTemplate () {
>>                     Memory32Fixed (ReadWrite, 0x80a40400, 0x00000200)
>>                     GpioInt (Level, ActiveHigh, Exclusive, PullNone, 0,
>>                         "\\_SB.PCI0.GPP5.FPGA") { 10 }
>>                 })
>>                 Name (_DSD, Package () {
>>                     ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>>                     Package () {
>>                        Package () { "compatible", "xlnx,axi-iic-2.1" },
>>                        Package () { "single-master", 1 },
>>                     }
>>                 })
>>             }
> 
> can you share more details about cpu and bootflow?
> 
> Thanks,
> Michal
> 

Hi Michal,

This is an AMD Ryzen Embedded V3C48 platform with Xilinx Artix 7 FPGA with multiple I2C and SPI IP blocks.

The FPGA sits on PCIE bus and has all the IP blocks memory mapped. I2C blocks also generate PCI MSI interrupts and we have implemented a custom irq_chip/gpio driver that creates the irq_domain hierarchy.

Adding these changes allowed us to benefit from the existing ACPI device enumeration in the kernel and re-use the existing drivers.

Thanks,
Abdurrahman