[PATCH v3 4/6] irqchip/gic-v5: Add ACPI IRS probing

[Jonathan Cameron]

On Thu, 15 Jan 2026 10:50:50 +0100
Lorenzo Pieralisi <lpieralisi at kernel.org> wrote:

> On ARM64 ACPI systems GICv5 IRSes are described in MADT sub-entries.
> 
> Add the required plumbing to parse MADT IRS firmware table entries and
> probe the IRS components in ACPI.
> 
> Augment the irqdomain_ops.translate() for PPI and SPI IRQs in order to
> provide support for their ACPI based firmware translation.
> 
> Implement an irqchip ACPI based callback to initialize the global GSI
> domain upon an MADT IRS detection.
> 
> The IRQCHIP_ACPI_DECLARE() entry in the top level GICv5 driver is only used
> to trigger the IRS probing (ie the global GSI domain is initialized once on
> the first call on multi-IRS systems); IRS probing takes place by calling
> acpi_table_parse_madt() in the IRS sub-driver, that probes all IRSes
> in sequence.
> 
> Add a new ACPI interrupt model so that it can be detected at runtime and
> distinguished from previous GIC architecture models.
> 
> Signed-off-by: Lorenzo Pieralisi <lpieralisi at kernel.org>
> Cc: Thomas Gleixner <tglx at kernel.org>
> Cc: "Rafael J. Wysocki" <rafael at kernel.org>
> Cc: Marc Zyngier <maz at kernel.org>
LGTM
Reviewed-by: Jonathan Cameron <jonathan.cameron at huawei.com>