[PATCH v3 2/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32

[Rodrigo Alencar]

On 25/10/31 03:30PM, Jun Guo wrote:
> The default FIFO data width of the Cadence SPI IP is 8 bits, but
> the hardware supports configurations of 16 bits and 32 bits.
> This patch enhances the driver to support communication with both
> 16-bits and 32-bits FIFO data widths.
> 
> Signed-off-by: Jun Guo <jun.guo at cixtech.com>

...

> +static inline void cdns_spi_writer(struct cdns_spi *xspi)
> +{
> +	u32 txw = 0;
> +
> +	if (xspi->txbuf && !IS_ALIGNED((uintptr_t)xspi->txbuf, xspi->n_bytes)) {
> +		pr_err("%s: txbuf address is not aligned for %d bytes\n",
> +		       __func__, xspi->n_bytes);
> +		return;
> +	}
> +
> +	if (xspi->txbuf) {
> +		switch (xspi->n_bytes) {
> +		case CDNS_SPI_N_BYTES_U8:
> +			txw = *(u8 *)xspi->txbuf;
> +			break;
> +		case CDNS_SPI_N_BYTES_U16:
> +			txw = *(u16 *)xspi->txbuf;
> +			break;
> +		case CDNS_SPI_N_BYTES_U32:
> +			txw = *(u32 *)xspi->txbuf;
> +			break;
> +		default:
> +			pr_err("%s invalid n_bytes %d\n", __func__,
> +			       xspi->n_bytes);
> +			return;
> +		}
> +		cdns_spi_write(xspi, CDNS_SPI_TXD, txw);
> +		xspi->txbuf = (u8 *)xspi->txbuf + xspi->n_bytes;
> +	}

cdns_spi_write(xspi, CDNS_SPI_TXD, txw) needs to be called regardless of xspi->txbuf.
Otherwise, there will be no clock for the read operation to work.
This is a bug I am seeing on a Zedboard running on 6.19

kind regards,

Rodrigo Alencar