[PATCH v2 06/11] arm: dts: stm32: introduce the debug bus for stm32mp1x platforms
Gatien Chevallier
gatien.chevallier at foss.st.com
Wed Jan 14 02:29:20 PST 2026
Some peripherals cannot be probed if a debug configuration is not set
in the BSEC.
Introduce a debug bus that will check the debug subsystem accessibility
before probing these peripheral drivers.
Add Coresight peripheral nodes under this bus and add the appropriate
access-controllers property to the HDP node.
Signed-off-by: Antonio Borneo <antonio.borneo at foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier at foss.st.com>
---
arch/arm/boot/dts/st/stm32mp131.dtsi | 118 ++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp151.dtsi | 172 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp153.dtsi | 68 ++++++++++++++
3 files changed, 358 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index b9657ff91c23..315c2a952f60 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue at foss.st.com> for STMicroelectronics.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
@@ -964,9 +965,126 @@ hdp: pinctrl at 5002a000 {
compatible = "st,stm32mp131-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
+ access-controllers = <&dbg_bus 1>;
status = "disabled";
};
+ dbg_bus: bus at 50080000 {
+ compatible = "st,stm32mp131-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ cs_etf: etf at 50092000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_tpiu: tpiu at 50093000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cs_cti_trace: cti at 50094000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+ };
+
+ cs_cti_cpu0: cti at 500d8000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d8000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns at 0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu0>;
+ };
+
+ trig-conns at 2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm0>;
+ };
+ };
+
+ cs_etm0: etm at 500dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+ };
+
mdma: dma-controller at 58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index b1b568dfd126..1559263204be 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre at st.com> for STMicroelectronics.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
@@ -274,9 +275,180 @@ hdp: pinctrl at 5002a000 {
compatible = "st,stm32mp151-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
+ access-controllers = <&dbg_bus 1>;
status = "disabled";
};
+ dbg_bus: bus at 50080000 {
+ compatible = "st,stm32mp151-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ cs_funnel: funnel at 50091000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x50091000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port at 0 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ remote-endpoint = <&stm_out_port>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_etf: etf at 50092000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_tpiu: tpiu at 50093000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cs_cti_trace: cti at 50094000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+ };
+
+ cs_stm: stm at 500a0000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x500a0000 0x00001000>,
+ <0x90000000 0x01000000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ stm_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ cs_cti_cpu0: cti at 500d8000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d8000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns at 0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu0>;
+ };
+
+ trig-conns at 2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm0>;
+ };
+ };
+
+ cs_etm0: etm at 500dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
+ };
+ };
+ };
+ };
+
mdma1: dma-controller at 58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi
index 92794b942ab2..17d52d93695e 100644
--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
@@ -30,6 +30,74 @@ timer {
};
};
+&cs_funnel {
+ in-ports {
+ port at 2 {
+ reg = <2>;
+ funnel_in_port2: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+};
+
+&dbg_bus {
+ cs_cti_cpu1: cti at 500d9000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d9000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns at 0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu1>;
+ };
+
+ trig-conns at 2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm1>;
+ };
+ };
+
+ cs_etm1: etm at 500dd000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dd000 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_in_port2>;
+ };
+ };
+ };
+ };
+};
+
&etzpc {
m_can1: can at 4400e000 {
compatible = "bosch,m_can";
--
2.43.0
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