[PATCH v2 4/5] clk: samsung: gs101: add support for Display Process Unit (DPU) clocks

[Peter Griffin]

Hi André,

On Mon, 12 Jan 2026 at 15:06, André Draszik <andre.draszik at linaro.org> wrote:
>
> On Mon, 2026-01-12 at 14:16 +0000, Peter Griffin wrote:
> > cmu_dpu is the clock management unit used for the Display Process Unit
> > block. It generates clocks for image scaler, compressor etc.
> >
> > Add support for the muxes, dividers and gates in cmu_dpu.
> >
> > Signed-off-by: Peter Griffin <peter.griffin at linaro.org>
> > ---
> > Changes in v2:
> >  - Update gout_dpu_dpu_pclk to gout_dpu_gpc_dpu_pclk (Peter)
> >  - Fix dout_dpu_busp parent (Peter)
> > ---
> >  drivers/clk/samsung/clk-gs101.c | 283 ++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 283 insertions(+)
> >
> > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> > index 8551289b46eb88ec61dd1914d0fe782ae6794000..b38c6c8749aae42319d2004ff5ffbc9a19320cac 100644
> > --- a/drivers/clk/samsung/clk-gs101.c
> > +++ b/drivers/clk/samsung/clk-gs101.c
> > @@ -25,6 +25,7 @@
> >  #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> >  #define CLKS_NR_PERIC0       (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> >  #define CLKS_NR_PERIC1       (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> > +#define CLKS_NR_DPU  (CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1)
>
> Between APM and HSI0 to keep alphabetic ordering :-)

will fix

>
> >
> >  #define GS101_GATE_DBG_OFFSET 0x4000
> >  #define GS101_DRCG_EN_OFFSET  0x104
> > @@ -4426,6 +4427,285 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> >       .drcg_offset            = GS101_DRCG_EN_OFFSET,
> >  };
> >
> > +/* ---- CMU_DPU ------------------------------------------------------------- */
>
> I'll do a full review later, but this new block should also be between
> existing CMU_APM and CMU_HSI0 blocks to keep alphabetic ordering.

Will fix.

Thanks,

Peter.