[PATCH] arm64: dts: amlogic: S4: fix SD card initialization failure

[neil.armstrong at linaro.org]

On 1/13/26 10:38, Nick Xie wrote:
> Jerome Brunet <jbrunet at baylibre.com> 于2026年1月13日周二 16:57写道：
>>
>> On mar. 13 janv. 2026 at 09:19, Nick Xie <xieqinick at gmail.com> wrote:
>>
>>> The SD controller (sd at fe08a000) requires a clock source capable of
>>> generating a 400kHz frequency for the identification phase.
>>>
>>> Currently, the sd node uses CLKID_SD_EMMC_B as clkin0 and CLKID_FCLK_DIV2
>>> as clkin1. Both of these are high-frequency clocks (e.g., ~1GHz).
>>
>> The reason you are having this problem is because CLKID_SD_EMMC_B does
>> not provide 400kHz by default on this platform. We have been operating
>> with this (weak) assumption so far ... and it was OK until now.
>>
>>> The internal divider of the SD controller is limited to a maximum value
>>> of 64 (2^6). With input frequencies significantly higher than 25.6MHz
>>> (400kHz * 64), the driver is unable to generate the required 400kHz
>>> clock, causing the probe to fail with -EINVAL.
>>>
>>> Fix this by reparenting clkin0 to the 24MHz XTAL clock, consistent with
>>> the configuration of the sdio and emmc nodes. This allows the divider
>>> to successfully generate 400kHz (24MHz / 60).
>>>
>>
>> DT generally describe what the HW is, not how you wish to configure it.
>>
>> What you are doing here does not reparent anything. You are actually
>> mis-representing the clock tree, making the MMC device believe it has
>> 24MHz on its clkin0, even-though what it is really has still is
>> CLKID_SD_EMMC_B (presumably running a 1GHz)
>>
>> So if my understanding is correct, you are indeed setting the divider to
>> 60 instead of 64, but you are still dividing 1GHz so what you actually
>> get it 16,6MHz
>>
>> If you want to get 24MHz the clkin0, we need to assign the rate,
>> something we probably should have done before.
>>
>> I'll send something for this
>>
>>> Verified on Khadas VIM1S with SoC S4 S905Y4.
>>>
>>> Fixes: 3ab9d54b5d847 ("arm64: dts: amlogic: enable some device nodes for S4")
>>>
>>> Signed-off-by: Nick Xie <nick at khadas.com>
>>> ---
>>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>>> index 9d99ed2994dfa..b87bc83b5a9bb 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>>> @@ -833,7 +833,7 @@ sd: mmc at fe08a000 {
>>>                        reg = <0x0 0xfe08a000 0x0 0x800>;
>>>                        interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
>>>                        clocks = <&clkc_periphs CLKID_SDEMMC_B>,
>>> -                              <&clkc_periphs CLKID_SD_EMMC_B>,
>>> +                              <&xtal>,
>>>                                 <&clkc_pll CLKID_FCLK_DIV2>;
>>>                        clock-names = "core", "clkin0", "clkin1";
>>>                        resets = <&reset RESET_SD_EMMC_B>;
>>
>> --
>> Jerome
> 
> Hello Jerome,
> 
> Thanks for your review.
> 
> I also checked the Amlogic 5.15 vendor kernel [1], it also use xtal as clkin0.
> 
> [1] - https://github.com/khadas/common_drivers/blob/khadas-vims-5.15.y/arch/arm64/boot/dts/amlogic/meson-s4.dtsi#L1358

OK looking at the driver, they reference mux0 (CLKID_SD_EMMC_B_CLK_MUX) & mux1 (CLKID_SD_EMMC_B_CLK) and they set parent of mux0, clkin0 (xtal) which is exactly what Jerome said:
https://github.com/khadas/common_drivers/blob/e9cec30b94864f4f3518cc492940690709a5075b/drivers/mmc/host/meson-gx-mmc.c#L751

We need to assign the rate of clkin0 to a low enough rate for the internal divider of the SD controller
to achieve 400KHz.

Neil