[PATCH] usb: dwc3: Always deassert xilinx resets

[Thinh Nguyen]

On Fri, Jan 09, 2026, Pandey, Radhey Shyam wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
> 
> > -----Original Message-----
> > From: Thinh Nguyen <Thinh.Nguyen at synopsys.com>
> > Sent: Friday, January 9, 2026 6:19 AM
> > To: Sean Anderson <sean.anderson at linux.dev>
> > Cc: Thinh Nguyen <Thinh.Nguyen at synopsys.com>; open list:DESIGNWARE
> > USB3 DRD IP DRIVER <linux-usb at vger.kernel.org>; Frager, Neal
> > <neal.frager at amd.com>; Simek, Michal <michal.simek at amd.com>; open list
> > <linux-kernel at vger.kernel.org>; moderated list:ARM/ZYNQ ARCHITECTURE
> > <linux-arm-kernel at lists.infradead.org>; Philipp Zabel <p.zabel at pengutronix.de>;
> > Pandey, Radhey Shyam <radhey.shyam.pandey at amd.com>; Greg Kroah-Hartman
> > <gregkh at linuxfoundation.org>
> > Subject: Re: [PATCH] usb: dwc3: Always deassert xilinx resets
> >
> > On Tue, Jan 06, 2026, Sean Anderson wrote:
> > > If we don't have a usb3 phy we don't need to assert the core resets.
> > > Deassert them even if we didn't assert them to support booting when
> > > the bootloader never released the core from reset.
> Is it a customized bootloader ? i.e it assert reset but don't deassert.
> 
> I think ideally core /APB reset should be done independent on
> MAC 2.0/3.0 configuration. Not sure where the recommendation is
> coming from to only do it for 3.0 MAC. Let me check the IP spec.
> Thinh: Please chime in with your thoughts.
> 

The dwc3 programming flow initiating the soft reset has not changed. How
each platform handles SoC specific resets at initialization varies
between implementation. I reviewed the change base on what's available
in the current code and the commit messages, and it sounded reasonable
to me. You may know more about this platform to provide better feedback
to Sean.

BR,
Thinh