[PATCH v3 35/36] KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest

[Jonathan Cameron]

On Fri, 9 Jan 2026 17:04:50 +0000
Sascha Bischoff <Sascha.Bischoff at arm.com> wrote:

> This basic selftest creates a vgic_v5 device (if supported), and tests
> that one of the PPI interrupts works as expected with a basic
> single-vCPU guest.
> 
> Upon starting, the guest enables interrupts. That means that it is
> initialising all PPIs to have reasonable priorities, but marking them
> as disabled. Then the priority mask in the ICC_PCR_EL1 is set, and
> interrupts are enable in ICC_CR0_EL1. At this stage the guest is able
> to receive interrupts. The architected SW_PPI (64) is enabled and
> KVM_IRQ_LINE ioctl is used to inject the state into the guest.
> 
> The guest's interrupt handler has an explicit WFI in order to ensure
> that the guest skips WFI when there are pending and enabled PPI
> interrupts.
> 
> Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
Seems fine to me, but I'm not that familiar with the self test elements, so
hopefully someone who is will review as well.

Reviewed-by: Jonathan Cameron <jonathan.cameron at huawei.com>