[PATCH v3 22/36] KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes

[Jonathan Cameron]

On Fri, 9 Jan 2026 17:04:46 +0000
Sascha Bischoff <Sascha.Bischoff at arm.com> wrote:

> A guest should not be able to detect if a PPI that is not exposed to
> the guest is implemented or not. Avoid the guest enabling any PPIs
> that are not implemented as far as the guest is concerned by trapping
> and masking writes to the two ICC_PPI_ENABLERx_EL1 regisers.

registers

> 
> When a guest writes these registers, the write is masked with the set
> of PPIs actually exposed to the guest, and the state is written back
> to KVM's shadow state. As there is now no way for the guest to change
> the PPI enable state without it being trapped, saving of the PPI
> Enable state is dropped from guest exit.
> 
> Reads for the above registers are not masked. When the guest is
> running and reads from the above registers, it is presented with what
> KVM provides in the ICH_PPI_ENABLERx_EL2 registers, which is the
> masked version of what the guest last wrote.
> 
> Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>

Seems fine to me.
Reviewed-by: Jonathan Cameron <jonathan.cameron at huawei.com>