[PATCH v1 1/2] dt-bindings: ethernet: eswin: add clock sampling control

[Andrew Lunn]

>    rx-internal-delay-ps:
> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +    enum: [0, 20, 60, 100, 200, 400, 800, 1600, 2400]
>  
>    tx-internal-delay-ps:
> -    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> +    enum: [0, 20, 60, 100, 200, 400, 800, 1600, 2400]

You need to add some text to the Changelog to indicate why this is
safe to do, and will not cause any regressions for DT blobs already in
use. Backwards compatibility is very important and needs to be
addressed.

> +  eswin,rx-clk-invert:
> +    description:
> +      Invert the receive clock sampling polarity at the MAC input.
> +      This property may be used to compensate for SoC-specific
> +      receive clock to data skew and help ensure correct RX data
> +      sampling at high speed.
> +    type: boolean

This does not make too much sense to me. The RGMII standard indicates
sampling happens on both edges of the clock. The rising edge is for
the lower 4 bits, the falling edge for the upper 4 bits. Flipping the
polarity would only swap the nibbles around.

	Andrew