[PATCH v2] arm64: errata: Workaround for SI L1 downstream coherency issue

Jason Gunthorpe jgg at nvidia.com
Thu Jan 8 08:54:14 PST 2026


On Thu, Jan 08, 2026 at 04:41:47PM +0000, Robin Murphy wrote:

> The point is that if there's a coherent interconnect downstream of the SMMU
> - which we infer from the SMMU's own coherency - then we should be able to
> make the *output* of SMMU translation coherent,

Sadly I'm aware of HW where that isn't true..

The SMMU is flexible and there are more than one fabric connection
from a SW visible SMMU instance. They can have different properties.

Especially if the design is focused on something like isochronous real
time guarentees.

Jason



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