[PATCH] pwm: stm32: handle polarity change when PWM is enabled

[Uwe Kleine-König]

Hey Sean,

On Tue, Jan 06, 2026 at 11:30:34AM +0000, Sean Nyekjaer wrote:
> On Tue, Jan 06, 2026 at 11:22:57AM +0100, Uwe Kleine-König wrote:
> > On Tue, Jan 06, 2026 at 08:01:57AM +0100, Sean Nyekjaer wrote:
> > > After commit 7346e7a058a2 ("pwm: stm32: Always do lazy disabling"),
> > > polarity changes are ignored. Updates to the TIMx_CCER CCxP bits are
> > > ignored by the hardware when the master output is enabled via the
> > > TIMx_BDTR MOE bit.
> > [...]
> > I have hardware using this driver, will set it up later this week for
> > testing.
> 
> Very cool, looking forward to hear if you can re-produce.

I cannot. I have:

	# uname -r
	6.11.0-rc1-00028-geb18504ca5cf-dirty

(the -dirty is only from enabling the pwm for my machine, no driver
changes)

	# cat /sys/kernel/debug/pwm
	0: platform/40001000.timer:pwm, 4 PWM devices
	...
	 pwm-3   (sysfs               ): requested enabled period: 313720 ns duty: 10000 ns polarity: normal

and pulseview/sigrok detects 3.187251% with a period of 313.8 µs.

After

	echo inversed > /sys/class/pwm/pwmchip0/pwm3/polarity

the output changes to

	# cat /sys/kernel/debug/pwm
	0: platform/40001000.timer:pwm, 4 PWM devices
	...
	 pwm-3   (sysfs               ): requested enabled period: 313720 ns duty: 10000 ns polarity: inverse

and pulseview/sigrok claims 96.812749% with a period of 313.8 µs.
So the polarity change happend as expected.

This is on an st,stm32mp135f-dk board.

Where is the difference to your observations?

Best regards
Uwe
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