[PATCH v2] dt-bindings: usb: Add Socionext Uniphier DWC3 controller
Kunihiko Hayashi
hayashi.kunihiko at socionext.com
Mon Jan 5 20:33:56 PST 2026
Hi Rob,
On 2026/01/06 1:24, Rob Herring (Arm) wrote:
> The Socionext Uniphier DWC3 controller binding is already in use, but
> undocumented. It's a straight-forward binding similar to other DWC3
> bindings.
>
> Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
> ---
> v2:
> - Allow 1 phy entry for Pro4
> ---
> .../bindings/usb/socionext,uniphier-dwc3.yaml | 89 +++++++++++++++++++
> 1 file changed, 89 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/usb/socionext,uniphier-dwc3.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/usb/socionext,uniphier-dwc3.yaml
> b/Documentation/devicetree/bindings/usb/socionext,uniphier-dwc3.yaml
> new file mode 100644
> index 000000000000..2b253339c199
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/socionext,uniphier-dwc3.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/socionext,uniphier-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Socionext Uniphier SuperSpeed DWC3 USB SoC controller
> +
> +maintainers:
> + - Kunihiko Hayashi <hayashi.kunihiko at socionext.com>
> + - Masami Hiramatsu <mhiramat at kernel.org>
> +
> +select:
> + properties:
> + compatible:
> + contains:
> + const: socionext,uniphier-dwc3
> + required:
> + - compatible
> +
> +properties:
> + compatible:
> + items:
> + - const: socionext,uniphier-dwc3
> + - const: snps,dwc3
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 1
> + items:
> + - description: Host or single combined interrupt
> + - description: Peripheral interrupt
> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - enum:
> + - dwc_usb3
> + - host
> + - const: peripheral
> +
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: ref
> + - const: bus_early
> + - const: suspend
> +
> + phys:
> + description: 1 to 4 HighSpeed PHYs followed by 1 or 2 SuperSpeed PHYs
> + minItems: 1
> + maxItems: 6
> +
> + resets:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> +
> +unevaluatedProperties: false
> +
> +allOf:
> + - $ref: snps,dwc3.yaml#
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + usb at 65a00000 {
> + compatible = "socionext,uniphier-dwc3", "snps,dwc3";
> + reg = <0x65a00000 0xcd00>;
> + interrupt-names = "dwc_usb3";
> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "ref", "bus_early", "suspend";
> + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
> + resets = <&usb0_rst 15>;
> + phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
> + <&usb0_ssphy0>, <&usb0_ssphy1>;
> + dr_mode = "host";
> + };
I've checked this with ARCH=arm and ARCH=arm64.
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko at socionext.com>
Thank you,
---
Best Regards
Kunihiko Hayashi
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