[PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (fixes)
by Paul Walmsley <pjw at kernel.org>:

On Tue, 18 Aug 2026 17:10:00 +0800 you wrote:
> The available-counter mask was a single unsigned long, but iteration
> uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object.
> Filling with an unsigned-long bit at index 32 and above is also wrong.
> 
> Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word
> into CFG_MATCH when checking events, when allocating an index, and when
> stopping all counters. Set the counter base to i times BITS_PER_LONG.
> Share the CFG_MATCH ecall through a small helper so the 32-bit argument
> split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits
> above XLEN set, so the first word alone is not enough.
> 
> [...]

Here is the summary with links:
  - [v2,2/2] perf: RISC-V: store available counter mask as bitmap
    https://git.kernel.org/riscv/c/e7bdbf5131ff
  - [v2,1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks
    (no matching commit)

You are awesome, thank you!
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