[PATCH v1 1/4] dt-bindings: Add CIX Sky1 USB bindings
Conor Dooley
conor at kernel.org
Mon Aug 31 09:07:36 PDT 2026
On Mon, Aug 31, 2026 at 04:23:05PM +0800, Hongliang Yang wrote:
> Add device tree bindings for CIX Sky1 USB3 PHY and Cadence USBSSP
> controller glue layer.
>
> Signed-off-by: Hongliang Yang <hongliang.yang at cixtech.com>
> ---
> .../bindings/phy/cix,sky1-usb3-phy.yaml | 109 +++++++++++++
> .../bindings/usb/cix,sky1-usbssp.yaml | 153 ++++++++++++++++++
Two patches please.
> MAINTAINERS | 3 +
> 3 files changed, 265 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
> new file mode 100644
> index 000000000000..76d020df72dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/cix,sky1-usb3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CIX Sky1 USB3 PHY
> +
> +maintainers:
> + - Hongliang Yang <hongliang.yang at cixtech.com>
> +
> +description:
> + The CIX Sky1 USB3 PHY is a multi-port SuperSpeedPlus PHY that
> + supports up to two USB3 lanes. Each port is represented as a
> + child node of the PHY controller.
> +
> +properties:
> + compatible:
> + const: cix,sky1-usb3-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: APB register interface clock
> + - description: PHY reference clock
> +
> + clock-names:
> + items:
> + - const: apb_clk
> + - const: ref_clk
drop "_clk", they're both clocks..
pw-bot: changes-requested
> +
> + resets:
> + items:
> + - description: PHY reset
> + - description: PHY APB preset
> +
> + reset-names:
> + items:
> + - const: reset
> + - const: preset
drop "reset" from here, they're both resets. Call them "core" and "apb"
or something instead.
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +patternProperties:
> + "^usb-port@[0-9a-f]+$":
> + type: object
> + description:
> + A single USB3 PHY port/lane.
> +
> + properties:
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + required:
> + - reg
> + - "#phy-cells"
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - "#address-cells"
> + - "#size-cells"
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/cix,sky1.h>
> + #include <dt-bindings/reset/cix,sky1-s5-system-control.h>
> +
> + usb-phy at 9210000 {
> + compatible = "cix,sky1-usb3-phy";
> + reg = <0x09210000 0x40000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>,
> + <&s5_syscon SKY1_USBPHY_SS_PST_N>;
> + reset-names = "reset", "preset";
> +
> + clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>,
> + <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>;
> + clock-names = "apb_clk", "ref_clk";
> +
> + usb-port at 0 {
> + reg = <0>;
> + #phy-cells = <0>;
> + };
> +
> + usb-port at 1 {
> + reg = <1>;
> + #phy-cells = <0>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
> new file mode 100644
> index 000000000000..47202ff5b9e5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
> @@ -0,0 +1,153 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/cix,sky1-usbssp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CIX Sky1 Cadence USBSSP Controller
> +
> +maintainers:
> + - Hongliang Yang <hongliang.yang at cixtech.com>
> +
> +description:
> + The CIX Sky1 USBSSP controller is based on the Cadence USBSSP DRD
> + controller. The integration adds glue registers and mode strap controls
> + in the Sky1 S5 system controller. The CIX glue node wraps a Cadence
> + USBSSP core as a child node.
> +
> +properties:
> + compatible:
> + const: cix,sky1-usbssp
> +
> + reg:
> + items:
> + - description: AXI property configuration register
> + - description: Controller status register
> +
> + reg-names:
> + items:
> + - const: axi_property
> + - const: controller_status
> +
> + clocks:
> + items:
> + - description: Start-of-frame clock
> + - description: AXI bus clock
> + - description: Low-power mode clock
> + - description: APB register interface clock
> +
> + clock-names:
> + items:
> + - const: sof_clk
> + - const: usb_aclk
> + - const: lpm_clk
> + - const: usb_pclk
Same stuff here on naming
> +
> + resets:
> + items:
> + - description: APB register reset
> + - description: Controller reset
> +
> + reset-names:
> + items:
> + - const: usb_preset
> + - const: usb_reset
and here.
> +
> + cix,usb_syscon:
No underscores in property names.
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the Sky1 S5 system controller used to program USB mode
> + strap controls.
> +
> + axi_bmax_value:
Missing vendor prefix.
No underscores in property names.
Why is this not a fixed value per SoC?
Cheers,
Conor.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x7
> + description:
> + AXI bus maximum burst length configuration value.
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
> +
> +patternProperties:
> + "^usb-controller@[0-9a-f]+$":
> + $ref: cdns,usb3.yaml#
> + description:
> + The Cadence USBSSP core controller node. See cdns,usb3.yaml
> + for properties such as dr_mode, maximum-speed, phys, and interrupts.
> + unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - cix,usb_syscon
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/cix,sky1.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/reset/cix,sky1-s5-system-control.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + usb at 91c0300 {
> + compatible = "cix,sky1-usbssp";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + reg = <0x00 0x091c0314 0x00 0x4>,
> + <0x00 0x091c0400 0x00 0x4>;
> + reg-names = "axi_property", "controller_status";
> +
> + resets = <&src SKY1_USBC_SS2_PRST_N>,
> + <&src SKY1_USBC_SS2_RST_N>;
> + reset-names = "usb_preset", "usb_reset";
> +
> + clocks = <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>,
> + <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>,
> + <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>,
> + <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>;
> + clock-names = "sof_clk", "usb_aclk", "lpm_clk", "usb_pclk";
> +
> + cix,usb_syscon = <&src>;
> + axi_bmax_value = <0x7>;
> +
> + usb-controller at 91d0000 {
> + compatible = "cdns,usb3";
> + reg = <0x00 0x91d0000 0x00 0x4000>,
> + <0x00 0x91d8000 0x00 0x8000>,
> + <0x00 0x91d4000 0x00 0x4000>;
> + reg-names = "otg", "xhci", "dev";
> +
> + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "host", "peripheral", "otg", "wakeup";
> +
> + /* Cadence USBSSP core properties - see cdns,usb3.yaml */
> + maximum-speed = "super-speed-plus";
> + dr_mode = "otg";
> +
> + phys = <&usb3_phy4_0>, <&usb2_phy6>;
> + phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
> + };
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 15011f5752a9..4c5f6cbe9124 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2775,8 +2775,11 @@ S: Maintained
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git
> F: Documentation/devicetree/bindings/arm/cix.yaml
> F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml
> +F: Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
> +F: Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
> F: arch/arm64/boot/dts/cix/
> F: drivers/mailbox/cix-mailbox.c
> +F: drivers/phy/cix/
> K: \bcix\b
>
> ARM/CLKDEV SUPPORT
> --
> 2.54.0
>
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