[PATCH] PCI: aspeed: fix clk and phy leak in aspeed_pcie_port_init error paths

[Manivannan Sadhasivam]

On Mon, 17 Aug 2026 01:16:33 +0800, Liu Zhenlong wrote:
> aspeed_pcie_port_init() calls clk_prepare_enable() to enable the port
> clock, but if phy_init() or phy_set_mode_ext() fails afterwards, the
> function returns without calling clk_disable_unprepare(), leaking the
> clock reference on every probe failure.  Additionally, when
> phy_set_mode_ext() fails, phy_init() has already succeeded, so
> phy_exit() is also missing, leaking the phy reference.
> 
> [...]

Applied, thanks!

[1/1] PCI: aspeed: fix clk and phy leak in aspeed_pcie_port_init error paths
      commit: 6c566177fc8f728271bed8018ac77b0a8199200d

Best regards,
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