[PATCH 1/7] iommu/arm-smmu-v3: Ensure L2 tables are visible before L1 ptrs

[Jason Gunthorpe]

On Fri, 28 Aug 2026 12:53:36 +0000, Mostafa Saleh <smostafa at google.com> wrote:
> Commit 6fabce53f6b9 ("iommu/arm-smmu-v3: Add a missing dma_wmb() for hitless STE update")
> adds a dma_wmb() to arm_smmu_write_entry() to make sure stream tables
> and context descriptors are observed first.
> 
> However, STE L1 table descriptors are configured directly
> via WRITE_ONCE(), where before that they were zeroed with memset()
> inside dma_direct_alloc() then written to abort in via memset() also
> in arm_smmu_init_initial_stes() without a barrier in both cases which
> means that the SMMUv3 can observe the allocated table before the
> written descriptors causing it to fetch random data.
> 
> [...]

Reviewed-by: Jason Gunthorpe <jgg at nvidia.com>

-- 
Jason