[PATCH net-next 3/3] net: phy: mediatek: support EcoNet EN751221 gbit SoC PHY

[Andrew Lunn]

> +static int en751221_tx_amp_compensation_tbl[2][TRANSFORMER_TYPE_MAX][MDI_TYPE_MAX][CALIB_CONST_TYPE_MAX][4] = {

const?

> +static u8 en751221_zcal_to_r50ohm[64] = {

const?

> +	125, 125, 125, 125, 125, 125, 124, 121, 118, 115, 112, 110, 108, 105, 103, 101,
> +	 99,  97,  95,  77,  75,  73,  72,  70,  68,  67,  65,  64,  63,  45,  44,  43,
> +	 41,  40,  39,  38,  37,  36,  35,  34,  32,  32,  31,  30,  13,  12,  11,  10,
> +	  9,   8,   8,   7,   6,   5,   5,   4,   3,   2,   2,   1,   0,   0,   0,   0
> +};

> +/* EN751221 also mirrors RG_BG_RASEL into CHIP SCU register 0x16c. */
> +static void en751221_gphy_mirror_rext(struct phy_device *phydev, u8 zcal)
> +{
> +	struct regmap *chip_scu;
> +
> +	chip_scu = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");

Does this need a change to the binding document?

> +static int en751221_gphy_config_init(struct phy_device *phydev)
> +{
> +	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);

Why is the EEE register being cleared?

> +
> +	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
> +	__mtk_tr_write(phydev, 0x1, 0xf, 0x00, 0x00002b);
> +	__mtk_tr_write(phydev, 0x1, 0xf, 0x03, 0x082422);
> +	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
> +
> +	ret = phy_write(phydev, MII_CTRL1000,
> +			ADVERTISE_1000FULL | CTL1000_PREFER_MASTER |
> +			CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);

What does this default to?

> +
> +	phy_set_bits(phydev, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE);

Why? config_aneg() will do this, if needed.

     Andrew