[PATCH 5/7] arm64: hibernate: use dcache_by_myline_op

[Bradley Morgan]

swsusp_arch_suspend_exit() used to open code its cache maintenance, but
the dcache_by_myline_op macro does everything that open coded version
did, including the ARM64_WORKAROUND_CLEAN_CACHE handling. So use it.

Since this was first written the macro got split, with the trailing DSB
moved out into a wrapper, so use dcache_by_myline_op_nosync here and
keep relying on the DSB that already sits after the restore loop. That
keeps this a true no-op.

Signed-off-by: Bradley Morgan <brads at mainlining.org>
Cc: Ard Biesheuvel <ardb at kernel.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: James Morse <james.morse at arm.com>
Cc: Marc Zyngier <maz at kernel.org>
Cc: Will Deacon <will at kernel.org>
---
 arch/arm64/kernel/hibernate-asm.S | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S
index 2baefe7a82d3..f7613404f99e 100644
--- a/arch/arm64/kernel/hibernate-asm.S
+++ b/arch/arm64/kernel/hibernate-asm.S
@@ -66,16 +66,11 @@ SYM_CODE_START(swsusp_arch_suspend_exit)
 
 	copy_page	x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
 
+	/* Clean the restored page to the PoU */
+	mov	x0, x10
 	add	x1, x10, #PAGE_SIZE
-	/* Clean the copied page to PoU - based on caches_clean_inval_pou() */
 	raw_dcache_line_size x2, x3
-	sub	x3, x2, #1
-	bic	x4, x10, x3
-2:	/* clean D line / unified line */
-alternative_insn "dc cvau, x4",  "dc civac, x4",  ARM64_WORKAROUND_CLEAN_CACHE
-	add	x4, x4, x2
-	cmp	x4, x1
-	b.lo	2b
+	dcache_by_myline_op_nosync cvau, x0, x1, x2, x3
 
 	ldr	x19, [x19, #HIBERN_PBE_NEXT]
 	cbnz	x19, 1b
-- 
2.47.3