[PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency

[Jason Gunthorpe]

On Tue, Aug 25, 2026 at 06:06:45PM +0100, Will Deacon wrote:
> The documentation for 3673557 gives a possible workaround of:
> 
>   - When invalidating a contiguous set of page tables, perform the
>     invalidation sequence twice. Only the invalidation sequence needs to
>     be performed twice, not the SYNC.
> 
> and we just merged something very similar from Ashish. Could we use that
> for domains that want to use contiguous ptes?

I figured out a way to bound it to at most 3 RILs (and that is rare,
mostly it is two RILs), so double invalidation would be at least 4
RILs using Robin's trick and way more using the existing algorithm.

So it would work but I'm happy enough with the 3 RIL path + SVA over
invalidation. I was just waiting for one testing result before posting
the series but it is on my github..

https://github.com/jgunthorpe/linux/tree/iommu_pt_arm64 

Jason