[PATCH v6 06/33] arm64: sysreg: Convert SPSR_ELx to automatic register generation

[Steffen Eiden]

On Thu, Aug 13, 2026 at 10:33:04AM +0100, Marc Zyngier wrote:
> On Wed, 12 Aug 2026 16:36:02 +0100,
> Steffen Eiden <seiden at linux.ibm.com> wrote:
> > 
> > Convert SPSR_EL{1, 2, 12} to automatic register generation as per
> > DDIO616 2026-06. No functional change.
> > 
> > Signed-off-by: Steffen Eiden <seiden at linux.ibm.com>
> > ---
> >  arch/arm64/include/asm/sysreg.h |  3 ---
> >  arch/arm64/tools/sysreg         | 48 +++++++++++++++++++++++++++++++++
> >  2 files changed, 48 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index 4bfdac9401bd..1aa601c95188 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> 
> [...]
> 
> > +Enum	4:0	M
> > +	0b0000	EL0
> > +	0b0100	EL1t
> > +	0b0101	EL1h
> > +	0b1000	EL2t
> > +	0b1001	EL2h
> 
> I think you need to be consistent with the way you represent things,
> as you are mixing two representations:
> 
> - either you have a separate M[4] representing PSTATE.nRW, and then
>   the M[3-0] enum is a 4 bit field (and for simplicity you only
>   describe the AArch64 ELs including EL3[th], which are missing here)
> 
> - or M is a 5 bit field and, and you represent everything as a 5 bit
>   enum, providing all the AArch32 modes and EL3.
> 
> The former matches the JSON, the latter is closer to the
> representation in older versions of the ARM ARM.
> 
> Pick one, stick to it.

Ok I'll do the first/JSON approach: 

...
Field	4	M4
Enum	3:0	M
	0b0000	EL0
	0b0100	EL1t
	0b0101	EL1h
	0b1000	EL2t
	0b1001	EL2h
	0b1100	EL3t
	0b1101	EL3h
EndEnum

	Steffen