[PATCH v2 06/15] dt-bindings: interconnect: Add Qualcomm Kuno NoC
Hardeep Sharma
hardeep.sharma at oss.qualcomm.com
Fri Aug 14 00:31:37 PDT 2026
Document the RPMh-based Network-on-Chip interconnect providers and
associated node-ID definitions for the Qualcomm Kuno SoC.
Signed-off-by: Hardeep Sharma <hardeep.sharma at oss.qualcomm.com>
---
.../bindings/interconnect/qcom,kuno-rpmh.yaml | 82 ++++++++++++++++++++
include/dt-bindings/interconnect/qcom,kuno.h | 89 ++++++++++++++++++++++
2 files changed, 171 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml
new file mode 100644
index 000000000000..ffbf14356f12
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,kuno-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on Kuno SoC
+
+maintainers:
+ - Hardeep Sharma <hardeep.sharma at oss.qualcomm.com>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also: include/dt-bindings/interconnect/qcom,kuno.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,kuno-aggre-noc
+ - qcom,kuno-clk-virt
+ - qcom,kuno-cnoc-main
+ - qcom,kuno-dc-noc
+ - qcom,kuno-mc-virt
+ - qcom,kuno-mem-noc
+ - qcom,kuno-pcie-anoc
+ - qcom,kuno-system-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,kuno-clk-virt
+ - qcom,kuno-mc-virt
+ then:
+ properties:
+ reg: false
+ clocks: false
+ clock-names: false
+ else:
+ required:
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ interconnect-clk-virt {
+ compatible = "qcom,kuno-clk-virt";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ interconnect at 1640000 {
+ compatible = "qcom,kuno-aggre-noc";
+ reg = <0x01640000 0x33400>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+...
diff --git a/include/dt-bindings/interconnect/qcom,kuno.h b/include/dt-bindings/interconnect/qcom,kuno.h
new file mode 100644
index 000000000000..eacbae38f85d
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,kuno.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H
+
+#define MASTER_SYS_TCU 0
+#define MASTER_LLCC 1
+#define MASTER_AUDIO 2
+#define MASTER_CPUCP 3
+#define MASTER_PCIE_RSCC 4
+#define MASTER_QDSS_BAM 5
+#define MASTER_QPIC 6
+#define MASTER_QUP_0 7
+#define MASTER_ANOC_SNOC 8
+#define MASTER_CNOC_DC_NOC 9
+#define MASTER_CNOC_SNOC 10
+#define MASTER_MSS_PROC 11
+#define MASTER_GEM_NOC_CFG 12
+#define MASTER_GEM_NOC_CNOC 13
+#define MASTER_GEM_NOC_PCIE_SNOC 14
+#define MASTER_ANOC_PCIE_GEM_NOC 15
+#define MASTER_SNOC_SF_MEM_NOC 16
+#define MASTER_QUP_CORE_0 17
+#define MASTER_CRYPTO 18
+#define MASTER_IPA 19
+#define MASTER_MSS_NAV 20
+#define MASTER_TME 21
+#define MASTER_APPSS_PROC 22
+#define MASTER_EMAC 23
+#define MASTER_IPA_PCIE 24
+#define MASTER_PCIE_0 25
+#define MASTER_QDSS_DAP 26
+#define MASTER_QDSS_ETR 27
+#define MASTER_QDSS_ETR_1 28
+#define MASTER_SDCC_4 29
+#define MASTER_USB3_0 30
+#define SLAVE_EBI1 31
+#define SLAVE_AHB2PHY 32
+#define SLAVE_AOSS 33
+#define SLAVE_APPSS 34
+#define SLAVE_AUDIO 35
+#define SLAVE_CLK_CTL 36
+#define SLAVE_RBCPR_CX_CFG 37
+#define SLAVE_RBCPR_MXA_CFG 38
+#define SLAVE_RBCPR_MXC_CFG 39
+#define SLAVE_CRYPTO_0_CFG 40
+#define SLAVE_EMAC_CFG 41
+#define SLAVE_IMEM_CFG 42
+#define SLAVE_IPA_CFG 43
+#define SLAVE_IPC_ROUTER_CFG 44
+#define SLAVE_LAGG_CFG 45
+#define SLAVE_MCCC_MASTER 46
+#define SLAVE_CNOC_MSS 47
+#define SLAVE_PCIE_0_CFG 48
+#define SLAVE_PCIE_RSC_CFG 49
+#define SLAVE_PDM 50
+#define SLAVE_PMU_WRAPPER_CFG 51
+#define SLAVE_PRNG 52
+#define SLAVE_QDSS_CFG 53
+#define SLAVE_QPIC 54
+#define SLAVE_QUP_0 55
+#define SLAVE_SDCC_4 56
+#define SLAVE_SPMI_VGI_COEX 57
+#define SLAVE_TCSR 58
+#define SLAVE_TLMM 59
+#define SLAVE_TME_CFG 60
+#define SLAVE_USB3 61
+#define SLAVE_VSENSE_CTRL_CFG 62
+#define SLAVE_A1NOC_CFG 63
+#define SLAVE_DDRSS_CFG 64
+#define SLAVE_LLCC 65
+#define SLAVE_GEM_NOC_CNOC 66
+#define SLAVE_SNOC_MEM_NOC_SF 67
+#define SLAVE_MEM_NOC_PCIE_SNOC 68
+#define SLAVE_ANOC_PCIE_GEM_NOC 69
+#define SLAVE_SNOC_CNOC 70
+#define SLAVE_ANOC_THROTTLE_CFG 71
+#define SLAVE_QUP_CORE_0 72
+#define SLAVE_BOOT_IMEM 73
+#define SLAVE_IMEM 74
+#define SLAVE_SERVICE_GEM_NOC 75
+#define SLAVE_PCIE_0 76
+#define SLAVE_QDSS_STM 77
+#define SLAVE_TCU 78
+
+#endif
--
2.43.0
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