[PATCH v5 08/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC

[Colin Huang via B4 Relay]

From: Andy Chung <Andy.Chung at amd.com>

Add the mctp-controller property to enable frontend NIC management
via PLDM over MCTP.
Also add EEPROM device for NIC FRU and reorder the I2C virtual bus
index accroding to the system silkscreen index.

Signed-off-by: Andy Chung <Andy.Chung at amd.com>
---
 .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts    | 119 +++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
index ff393ad7cdb7..703284721224 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
@@ -8,6 +8,25 @@ / {
 	compatible = "facebook,anacapa-bmc-evt2", "aspeed,ast2600";
 };
 
+&{/aliases} {
+	i2c36 = &i2c11mux0ch5;
+	i2c37 = &i2c11mux0ch6;
+	i2c38 = &i2c11mux0ch7;
+	i2c39 = &i2c11mux0ch0;
+	i2c40 = &i2c11mux0ch1;
+	i2c41 = &i2c11mux0ch2;
+	i2c42 = &i2c11mux0ch3;
+	i2c43 = &i2c11mux0ch4;
+	i2c44 = &i2c10mux0ch1;
+	i2c45 = &i2c10mux0ch2;
+	i2c46 = &i2c10mux0ch3;
+	i2c47 = &i2c10mux0ch4;
+	i2c48 = &i2c10mux0ch5;
+	i2c49 = &i2c10mux0ch6;
+	i2c50 = &i2c10mux0ch7;
+	i2c51 = &i2c10mux0ch0;
+};
+
 // MB - PDB
 &i2c8 {
 	i2c-mux at 72 {
@@ -55,6 +74,106 @@ eeprom at 51 {
 	};
 };
 
+// R Bridge Board
+&i2c10 {
+	multi-master;
+	mctp at 10 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	i2c-mux at 71 {
+		/delete-property/ i2c-mux-idle-disconnect;
+
+		i2c10mux0ch1: i2c at 1 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c10mux0ch2: i2c at 2 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c10mux0ch3: i2c at 3 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c10mux0ch4: i2c at 4 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+	};
+};
+
+// L Bridge Board
+&i2c11 {
+	multi-master;
+	mctp at 10 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	i2c-mux at 71 {
+		/delete-property/ i2c-mux-idle-disconnect;
+
+		i2c11mux0ch0: i2c at 0 {
+			mctp-controller;
+			// FE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c11mux0ch1: i2c at 1 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c11mux0ch2: i2c at 2 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c11mux0ch3: i2c at 3 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c11mux0ch4: i2c at 4 {
+			mctp-controller;
+			// BE NIC FRU
+			eeprom at 50 {
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+	};
+};
+
 // MB
 &i2c13 {
 	i2c-mux at 70 {

-- 
2.34.1