[PATCH v6 2/2] perf: Add Raspberry Pi 5 (BCM2712) AXI PMU support
Ian Rogers
irogers at google.com
Wed Aug 12 21:35:33 PDT 2026
Expand the Raspberry Pi AXI PMU driver to support Broadcom BCM2712
(Raspberry Pi 5) system monitors, PCIe RP1 Southbridge links, HEVC decoder,
and Cortex-A76 DSU L3 interconnects.
Signed-off-by: Ian Rogers <irogers at google.com>
---
drivers/perf/rpi_axi_pmu.c | 120 +++++++++++++++++++++++++++++++++++--
1 file changed, 115 insertions(+), 5 deletions(-)
diff --git a/drivers/perf/rpi_axi_pmu.c b/drivers/perf/rpi_axi_pmu.c
index f7e5520d02eb..4c1b19c6cc2e 100644
--- a/drivers/perf/rpi_axi_pmu.c
+++ b/drivers/perf/rpi_axi_pmu.c
@@ -867,19 +867,45 @@ PMU_EVENT_ATTR_STRING(usb_system_l2_wtrans, rpi_axi_pmu_event_usb_system_l2_wtra
/* --- RASPBERRY PI 5 (BCM2712) EXPANDED EVENT ALIASES ---------------------- */
/* PCIe 2.0 x4 RP1 Southbridge Link Bus Events & Stall Wait Cycles (bus=6, BCM2712_SB__PCIE_RP1) */
+PMU_EVENT_ATTR_STRING(pcie_rp1_atrans, rpi_axi_pmu_event_pcie_rp1_atrans, "monitor=0,bus=6,counter=0");
+PMU_EVENT_ATTR_STRING(pcie_rp1_atwait, rpi_axi_pmu_event_pcie_rp1_atwait, "monitor=0,bus=6,counter=1");
+PMU_EVENT_ATTR_STRING(pcie_rp1_wtrans, rpi_axi_pmu_event_pcie_rp1_wtrans, "monitor=0,bus=6,counter=2");
+PMU_EVENT_ATTR_STRING(pcie_rp1_wtwait, rpi_axi_pmu_event_pcie_rp1_wtwait, "monitor=0,bus=6,counter=3");
+PMU_EVENT_ATTR_STRING(pcie_rp1_rtrans, rpi_axi_pmu_event_pcie_rp1_rtrans, "monitor=0,bus=6,counter=4");
+PMU_EVENT_ATTR_STRING(pcie_rp1_rtwait, rpi_axi_pmu_event_pcie_rp1_rtwait, "monitor=0,bus=6,counter=5");
/* HEVC (H.265) Hardware Video Decoder Bus Events (bus=7, BCM2712_SB__HEVC_DEC) */
+PMU_EVENT_ATTR_STRING(hevc_dec_atrans, rpi_axi_pmu_event_hevc_dec_atrans, "monitor=0,bus=7,counter=0");
+PMU_EVENT_ATTR_STRING(hevc_dec_wtrans, rpi_axi_pmu_event_hevc_dec_wtrans, "monitor=0,bus=7,counter=2");
+PMU_EVENT_ATTR_STRING(hevc_dec_rtrans, rpi_axi_pmu_event_hevc_dec_rtrans, "monitor=0,bus=7,counter=4");
/* Arm Cortex-A76 DSU L3 Interconnect Bus Events (bus=8, BCM2712_SB__A76_DSU_L3) */
+PMU_EVENT_ATTR_STRING(a76_dsu_l3_atrans, rpi_axi_pmu_event_a76_dsu_l3_atrans, "monitor=0,bus=8,counter=0");
+PMU_EVENT_ATTR_STRING(a76_dsu_l3_wtrans, rpi_axi_pmu_event_a76_dsu_l3_wtrans, "monitor=0,bus=8,counter=2");
+PMU_EVENT_ATTR_STRING(a76_dsu_l3_rtrans, rpi_axi_pmu_event_a76_dsu_l3_rtrans, "monitor=0,bus=8,counter=4");
/* VideoCore VII 3D Graphics Pipeline Bus Events (bus=10, BCM2712_SB__V3D7) */
+PMU_EVENT_ATTR_STRING(v3d7_atrans, rpi_axi_pmu_event_v3d7_atrans, "monitor=0,bus=10,counter=0");
+PMU_EVENT_ATTR_STRING(v3d7_wtrans, rpi_axi_pmu_event_v3d7_wtrans, "monitor=0,bus=10,counter=2");
+PMU_EVENT_ATTR_STRING(v3d7_rtrans, rpi_axi_pmu_event_v3d7_rtrans, "monitor=0,bus=10,counter=4");
/*
* Quad-Core Arm Cortex-A76 Cores 0-3 I-Cache & D-Cache Filtered Events
* (bus=14, BCM2712_SB__CPU_L2)
*/
+PMU_EVENT_ATTR_STRING(bcm2712_peripheral_rtrans, rpi_axi_pmu_event_bcm2712_peripheral_rtrans, "monitor=0,bus=12,counter=4");
+PMU_EVENT_ATTR_STRING(bcm2712_peripheral_wtrans, rpi_axi_pmu_event_bcm2712_peripheral_wtrans, "monitor=0,bus=12,counter=2");
+PMU_EVENT_ATTR_STRING(bcm2712_cpu_uc_rtrans, rpi_axi_pmu_event_bcm2712_cpu_uc_rtrans, "monitor=0,bus=13,counter=4");
+PMU_EVENT_ATTR_STRING(bcm2712_cpu_uc_wtrans, rpi_axi_pmu_event_bcm2712_cpu_uc_wtrans, "monitor=0,bus=13,counter=2");
/* BCM2712 Master ID Filtered Events */
+PMU_EVENT_ATTR_STRING(arm_rtrans, rpi_axi_pmu_event_arm_rtrans, "monitor=0,bus=14,counter=4,filter=10");
+PMU_EVENT_ATTR_STRING(arm_wtrans, rpi_axi_pmu_event_arm_wtrans, "monitor=0,bus=14,counter=2,filter=10");
+PMU_EVENT_ATTR_STRING(pcie0_rtrans, rpi_axi_pmu_event_pcie0_rtrans, "monitor=0,bus=6,counter=4,filter=15");
+PMU_EVENT_ATTR_STRING(pcie0_wtrans, rpi_axi_pmu_event_pcie0_wtrans, "monitor=0,bus=6,counter=2,filter=15");
+PMU_EVENT_ATTR_STRING(hvs_filtered_rtrans, rpi_axi_pmu_event_hvs_filtered_rtrans, "monitor=0,bus=9,counter=4,filter=22");
+PMU_EVENT_ATTR_STRING(emmc0_rtrans, rpi_axi_pmu_event_emmc0_rtrans, "monitor=0,bus=5,counter=4,filter=29");
+PMU_EVENT_ATTR_STRING(emmc0_wtrans, rpi_axi_pmu_event_emmc0_wtrans, "monitor=0,bus=5,counter=2,filter=29");
static struct attribute *rpi_axi_pmu_events_attrs[] = {
/* System Monitor events */
@@ -1039,11 +1065,37 @@ static struct attribute *rpi_axi_pmu_events_attrs[] = {
&rpi_axi_pmu_event_usb_system_l2_wtrans.attr.attr,
/* RPi 5 (BCM2712) Expanded Event Aliases */
-
-
-
-
-
+ &rpi_axi_pmu_event_pcie_rp1_atrans.attr.attr,
+ &rpi_axi_pmu_event_pcie_rp1_atwait.attr.attr,
+ &rpi_axi_pmu_event_pcie_rp1_wtrans.attr.attr,
+ &rpi_axi_pmu_event_pcie_rp1_wtwait.attr.attr,
+ &rpi_axi_pmu_event_pcie_rp1_rtrans.attr.attr,
+ &rpi_axi_pmu_event_pcie_rp1_rtwait.attr.attr,
+
+ &rpi_axi_pmu_event_hevc_dec_atrans.attr.attr,
+ &rpi_axi_pmu_event_hevc_dec_wtrans.attr.attr,
+ &rpi_axi_pmu_event_hevc_dec_rtrans.attr.attr,
+
+ &rpi_axi_pmu_event_a76_dsu_l3_atrans.attr.attr,
+ &rpi_axi_pmu_event_a76_dsu_l3_wtrans.attr.attr,
+ &rpi_axi_pmu_event_a76_dsu_l3_rtrans.attr.attr,
+
+ &rpi_axi_pmu_event_v3d7_atrans.attr.attr,
+ &rpi_axi_pmu_event_v3d7_wtrans.attr.attr,
+ &rpi_axi_pmu_event_v3d7_rtrans.attr.attr,
+
+ &rpi_axi_pmu_event_bcm2712_peripheral_rtrans.attr.attr,
+ &rpi_axi_pmu_event_bcm2712_peripheral_wtrans.attr.attr,
+ &rpi_axi_pmu_event_bcm2712_cpu_uc_rtrans.attr.attr,
+ &rpi_axi_pmu_event_bcm2712_cpu_uc_wtrans.attr.attr,
+
+ &rpi_axi_pmu_event_arm_rtrans.attr.attr,
+ &rpi_axi_pmu_event_arm_wtrans.attr.attr,
+ &rpi_axi_pmu_event_pcie0_rtrans.attr.attr,
+ &rpi_axi_pmu_event_pcie0_wtrans.attr.attr,
+ &rpi_axi_pmu_event_hvs_filtered_rtrans.attr.attr,
+ &rpi_axi_pmu_event_emmc0_rtrans.attr.attr,
+ &rpi_axi_pmu_event_emmc0_wtrans.attr.attr,
NULL,
};
@@ -1059,10 +1111,64 @@ static struct attribute *rpi_axi_pmu_events_attrs[] = {
*
* Return: attr->mode (0444) if visible on current SoC, 0 to hide.
*/
+static umode_t rpi_axi_pmu_events_is_visible(struct kobject *kobj,
+ struct attribute *attr, int unused)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct rpi_axi_pmu *rpi_pmu = pmu_to_rpi_axi_pmu(pmu);
+ struct perf_pmu_events_attr *pmu_attr;
+
+ pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
+
+ if (rpi_pmu->chip == CHIP_BCM2712) {
+ /*
+ * On RPi 5 (BCM2712), hide legacy VPU Mailbox IPC events (monitor=1)
+ * and legacy RPi 1-4 System Monitor aliases
+ */
+ if (strstr(pmu_attr->event_str, "monitor=1") ||
+ strstr(attr->name, "cpu0_") ||
+ strstr(attr->name, "cpu1_") ||
+ strstr(attr->name, "dma0_") ||
+ strstr(attr->name, "dma1_") ||
+ strstr(attr->name, "v3d0_") ||
+ strstr(attr->name, "v3d1_") ||
+ strstr(attr->name, "hvs_system") ||
+ strstr(attr->name, "isp_system") ||
+ strstr(attr->name, "usb_system") ||
+ strstr(attr->name, "ccp2tx_") ||
+ strstr(attr->name, "mphi_") ||
+ strstr(attr->name, "h264_") ||
+ strstr(attr->name, "v3d_") ||
+ (strstr(attr->name, "peripheral_") && !strstr(attr->name, "bcm2712_")) ||
+ (strstr(attr->name, "cpu_uc_") && !strstr(attr->name, "bcm2712_")) ||
+ strstr(attr->name, "cpu_l2_") ||
+ strstr(attr->name, "l2_control_") ||
+ strstr(attr->name, "system_control_") ||
+ strstr(attr->name, "direct_control_") ||
+ strstr(attr->name, "direct_data_"))
+ return 0;
+ } else {
+ /* On RPi 1-4 (BCM2835-BCM2711), hide RPi 5 specific events */
+ if (strstr(attr->name, "pcie_rp1") ||
+ strstr(attr->name, "a76_") ||
+ strstr(attr->name, "v3d7_") ||
+ strstr(attr->name, "hevc_dec") ||
+ strstr(attr->name, "arm_") ||
+ strstr(attr->name, "pcie0_") ||
+ strstr(attr->name, "hvs_filtered") ||
+ strstr(attr->name, "emmc0_") ||
+ strstr(attr->name, "bcm2712_"))
+ return 0;
+ }
+
+ return attr->mode;
+}
static const struct attribute_group rpi_axi_pmu_events_group = {
.name = "events",
.attrs = rpi_axi_pmu_events_attrs,
+ .is_visible = rpi_axi_pmu_events_is_visible,
};
/**
@@ -1954,6 +2060,10 @@ static const struct of_device_id rpi_axi_pmu_match[] = {
.compatible = "brcm,bcm2711-axiperf",
.data = (void *)CHIP_BCM2835,
},
+ {
+ .compatible = "brcm,bcm2712-axiperf",
+ .data = (void *)CHIP_BCM2712,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, rpi_axi_pmu_match);
--
2.55.0.691.gc56d675ccc-goog
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