[PATCH 0/7] irqchip/gic-v5: Misc fixes following sashiko's report

[Lorenzo Pieralisi]

While reviewing this series [1] sashiko spotted some issues [2] in the GICv5
host driver.

This short series addresses them along with other minor issues spotted
in the resulting code review following sashiko's report.

Issues short description:

* Check get_logical_index() return value in MADT IAFFID parsing that might cause
  out-of-bounds per CPU array indexing
* Add a check for !NULL LPI domain on LPI domain teardown
* Disable enabled IRSes on GICv5 driver probe failure
* Fix gicv5_init_common() error paths handling (clean-up paths were
  missing some runtime error conditions and clean-up)
* Release IRS iomem regions on OF probe and driver failures
* Fix smp_processor_id() usage on two preemptible code paths:
  - LPI/SPI IAFFID initialization
  - Dynamic L2 IST table entry initialization

This series depends (as in, applies cleanly on top) on [3] as reported with
the message-id tag.

[1] https://lore.kernel.org/kvm/20260810102652.758719-1-sascha.bischoff@arm.com
[2] https://sashiko.dev/#/message/20260810104747.E5CE71F000E9%40smtp.kernel.org
[3] https://lore.kernel.org/lkml/20260811152630.942023-1-sascha.bischoff@arm.com/

Signed-off-by: Lorenzo Pieralisi <lpieralisi at kernel.org>
---
Lorenzo Pieralisi (7):
      irqchip/gic-v5: Check get_logical_index() return value in MADT IAFFID parsing
      irqchip/gic-v5: Check for NULL LPI domain on domain teardown
      irqchip/gic-v5: Disable IRSes on probe failures
      irqchip/gic-v5: Fix gicv5_init_common() error paths
      irqchip/gic-v5: Release IRS iomem region on driver init failure
      irqchip/gic-v5: Use logical cpu 0 irs_data for dynamic IST allocation
      irqchip/gic-v5: Defer default SPI and LPI IAFFID programming

 drivers/irqchip/irq-gic-v5-irs.c   | 23 ++++++++++++++++++++++-
 drivers/irqchip/irq-gic-v5.c       | 28 +++++++++++-----------------
 include/linux/irqchip/arm-gic-v5.h |  2 ++
 3 files changed, 35 insertions(+), 18 deletions(-)
---
base-commit: 2ee859ebf156157609f71060ae472711c8cbc326
change-id: 20260811-gicv5-7-2-fixes-e9782feb68d5
prerequisite-message-id: <20260811152630.942023-1-sascha.bischoff at arm.com>
prerequisite-patch-id: 1e1b67496c67341e25a692236dfeff9526cddb97
prerequisite-patch-id: e5229c5d6aaef58620ff58b48c1c8122cf93ca9c

Best regards,
--  
Lorenzo Pieralisi <lpieralisi at kernel.org>