[PATCH v5 0/2] PCI: mediatek-gen3: Add 2-lanes mode support + clock

[Benjamin Larsson]

Hi.

On 10/08/2026 12:55, Christian Marangi (Ansuel) wrote:
> Il giorno lun 10 ago 2026 alle ore 12:33 Chen-Yu Tsai
> <wenst at chromium.org> ha scritto:
>>
>> On Fri, Aug 7, 2026 at 11:21 PM Bjorn Helgaas <helgaas at kernel.org> wrote:
>>>
>>> On Fri, Aug 07, 2026 at 11:24:09AM +0800, Chen-Yu Tsai wrote:
>>>> On Fri, Aug 7, 2026 at 12:53 AM Christian Marangi <ansuelsmth at gmail.com> wrote:
>>>>> This small series introduce support for 2-lanes mode for Airoha AN7581
>>>>
>>>> Just a nitpick, but I would probably name this something else, like
>>>> "cross-controller lane-bonding mode" or "lane stealing"? PCIe already
>>>> has 2x lanes as a standard feature, so this naming is a bit confusing.
>>>> It's not like dual-LVDS display in which LVDS is only a single lane.
>>>
>>> I suggested the "2-lane" and "x2" terminology because I assumed the
>>> result is what the PCIe spec would describe as a "x2 Link" consisting
>>> of two Lanes.
>>>
>>> If that's not the case, maybe "cross-controller lane-bonding mode" or
>>> "lane stealing" would be more accurate, but I don't know what those
>>> mean, so if we use them I would also like to know what the result
>>> looks like in standard PCIe terms.
>>
>> Benjamin pointed out later in the thread that it is just bifurcation.
>>
> 
> Yes but as me, you, Benjamin and Bjorn people who weren't there with the HW
> team at times the SoC was created, and given how the internal documentation
> these are just assumption and observation... Everyone can be correct and wrong.
> 
>> I would assume "PCIe bifurcation" is a standard term, so maybe we could
>> call this "Support un-bifurcated 2-lane operation"?
>>
> 
> And how coming from PCIe bifurcation to un-bifurcated 2-lane operation keeps
> the standard meaning?
> 
> This terms is equally custom as the previous "cross-controller
> lane-bonding mode"
> and "lane stealing"
> 
> I want to be honest... I'm not following why we are trying in every
> way possible to find
> a standard meaning for an highly integrated PCIe controller for a vendor SoC.
> It's not like there are devices shipped with PCIe slot where you can
> insert whatever
> card you want. (there is only a single RFB board but that is really to
> debug stuff and
> develop)
> 
> The SoC is designed to have WiFi cards attached and only a subset of them.
> And some of them require 2 lanes mode to work with this special configuration.
> 
> Even the DT bindings are not that specific to the details... at the
> end of the day
> everything is modelled as simple as "num-lanes = <2>;"
> 
Hi, I agree with Christian here. The property num-lanes will be able to 
describe all possible pcie configurations of the AN7581 and AN7563 SoCs 
(the AN7563 is using the same pci controller if I understand things 
correctly). Adding more properties will not make it less complex.

MvH
Benjamin Larsson