[PATCH v2 0/2] irqchip/gic-v5: GICv5 KVM IRS review fixes

[Sascha Bischoff]

Hi all,

v1 [1] combined irqchip and KVM fixes identified by Sashiko [2] while
reviewing the GICv5 KVM IRS series [3]. Following feedback, v2 splits
the fixes into separate irqchip and KVM postings. This posting
contains the irqchip fixes; the KVM fixes are posted separately.

Changes since v1:

* Split the combined series into irqchip and KVM postings.

* Dropped the setting of a CPU's IAFFID to 0 on clear as this might be a valid
  IAFFID.

* Added a reviewed by tag to "irqchip/gic-v5: Clear per-CPU IRS data
  on teardown".

The fixes are:

* Clear the per-CPU IRS pointer and IAFFID state when host IRS
  initialisation fails or an IRS is removed. This prevents the per-CPU
  state from retaining a pointer to freed IRS data.

* Add an isb() after disabling the GICv5 CPU interface. This ensures
  that interrupts are disabled before the helper returns.

These changes are based on v7.2-rc7.

Thanks,
Sascha

[1] https://lore.kernel.org/all/20260810102652.758719-1-sascha.bischoff@arm.com/
[2] https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff%40arm.com
[3] https://lore.kernel.org/all/20260724104819.1296803-1-sascha.bischoff@arm.com/

Sascha Bischoff (2):
  irqchip/gic-v5: Clear per-CPU IRS data on teardown
  irqchip/gic-v5: Synchronize CPU interface disable

 drivers/irqchip/irq-gic-v5-irs.c | 15 +++++++++++++++
 drivers/irqchip/irq-gic-v5.c     |  1 +
 2 files changed, 16 insertions(+)

-- 
2.34.1