[PATCH] arm64: dts: renesas: beacon: Specify ethernet PHY reset timings

[Geert Uytterhoeven]

On Tue, 14 Jul 2026 at 15:05, Marek Vasut
<marek.vasut+renesas at mailbox.org> wrote:
> The KSZ9131RNX reference manual [1] DS00002841D page 131 FIGURE 6-2:
> POWER SEQUENCE TIMING INTERNAL REGULATORS does not indicate how long
> should the system wait after deassertion of the PHY reset and before
> starting communication with the PHY via MDIO. Opt for the same value
> as used for KSZ9031RNX, which is 300 us.
>
> The KSZ9131RNX reference manual [1] DS00002841D page 131 FIGURE 6-2:
> POWER SEQUENCE TIMING INTERNAL REGULATORS row tSR Stable supply
> voltages to de-assertion of reset is at minimum 10 ms. Set DT
> property reset-assert-us to 10ms because the KSZ9131RNX RM does
> not explicitly spell out how long the reset has to be asserted,
> but this at least covers the worst case scenario.
>
> [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/00002841D.pdf
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>


Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
i.e. will queue in renesas-devel for v7.4.
Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds