[PATCH v5 03/10] phy: rockchip: samsung-hdptx: Guard against clk rate integer underflow

[Manivannan Sadhasivam]

On Thu, Jul 23, 2026 at 10:41:46PM +0300, Cristian Ciocaltea wrote:
> The 'fout' subtraction in rk_hdptx_phy_clk_calc_rate_from_pll_cfg()
> could result in an integer underflow, if the hardware registers are
> misconfigured or contain uninitialized values, such that the computed
> sigma-delta modulator offset sdm exceeds the base frequency fout.
> 
> This might lead to an absurdly high clock rate being returned to the
> Common Clock Framework, with unpredictable effects on downstream clk
> consumers.
> 
> Provide the necessary sanitization to avoid trusting the hardware state.
> 
> Reported-by: Sashiko <sashiko-bot at kernel.org>
> Closes: https://lore.kernel.org/all/20260611235702.0E9691F000E9@smtp.kernel.org/
> Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from PLL config")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
> ---
>  drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 44e99343f249..fcf04e9814cc 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -2280,10 +2280,16 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx)
>  		sdm = div_u64(PLL_REF_CLK * ropll_hw.sdc_deno *
>  			      ropll_hw.pms_mdiv * ropll_hw.sdm_num, val);
>  
> -		if (ropll_hw.sdm_num_sign)
> +		if (ropll_hw.sdm_num_sign) {
> +			if (sdm > fout) {
> +				dev_dbg(hdptx->dev, "Invalid ROPLL hw state: sdm > fout\n");

Same comment as previous patch.

- Mani

-- 
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