[PATCH v5 41/49] KVM: selftests: Add VGICv5 NR_IRQS attribute tests
Sascha Bischoff
Sascha.Bischoff at arm.com
Fri Aug 7 04:33:29 PDT 2026
Add coverage for the VGICv5 NR_IRQS attribute. VGICv5 exposes a
userspace-selectable SPI count, and KVM must reject values outside its
supported range or values that would change the interrupt layout after
it has been fixed.
Verify that the attribute defaults to zero before initialisation,
rejects too few SPIs, non-32-aligned counts, and a 32-aligned count
beyond the 1024-SPI maximum. Also verify that the maximum count is
accepted and can be initialised, that the selected count is reported,
that initialisation selects the default count, and that subsequent
changes are rejected.
Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
---
tools/testing/selftests/kvm/arm64/vgic_v5.c | 190 +++++++++++++++-----
1 file changed, 142 insertions(+), 48 deletions(-)
diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c b/tools/testing/selftests/kvm/arm64/vgic_v5.c
index 51ea2fe7141ad..f4c0d2c003bb4 100644
--- a/tools/testing/selftests/kvm/arm64/vgic_v5.c
+++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c
@@ -13,6 +13,8 @@
#include "vgic.h"
#define NR_VCPUS 1
+#define VGIC_V5_DEFAULT_NR_SPIS 32
+#define VGIC_V5_MAX_NR_SPIS BIT(16)
static u64 max_phys_size;
@@ -27,6 +29,63 @@ struct vm_gic {
#define GUEST_CMD_IS_AWAKE 12
#define GUEST_CMD_IS_READY 13
+static void guest_irq_handler(struct ex_regs *regs)
+{
+ bool valid;
+ u32 hwirq;
+ u64 ia;
+ static int count;
+
+ /*
+ * We have pending interrupts. Should never actually enter WFI
+ * here!
+ */
+ wfi();
+ GUEST_SYNC(GUEST_CMD_IS_AWAKE);
+
+ ia = gicr_insn(CDIA);
+ valid = GICV5_GICR_CDIA_VALID(ia);
+
+ GUEST_SYNC(GUEST_CMD_IRQ_CDIA);
+
+ if (!valid)
+ return;
+
+ gsb_ack();
+ isb();
+
+ hwirq = FIELD_GET(GICV5_GICR_CDIA_INTID, ia);
+
+ gic_insn(hwirq, CDDI);
+ gic_insn(0, CDEOI);
+
+ GUEST_SYNC(GUEST_CMD_IRQ_DIEOI);
+
+ if (++count >= 2)
+ GUEST_DONE();
+
+ /* Ask for the next interrupt to be injected */
+ GUEST_SYNC(GUEST_CMD_IS_READY);
+}
+
+static void guest_code(void)
+{
+ local_irq_disable();
+
+ gicv5_cpu_enable_interrupts();
+ local_irq_enable();
+
+ /* Enable the SW_PPI (3) */
+ write_sysreg_s(BIT_ULL(3), SYS_ICC_PPI_ENABLER0_EL1);
+
+ /* Ask for the first interrupt to be injected */
+ GUEST_SYNC(GUEST_CMD_IS_READY);
+
+ /* Loop forever waiting for interrupts */
+ for (;;)
+ cpu_relax();
+}
+
/* we don't want to assert on run execution, hence that helper */
static int run_vcpu(struct kvm_vcpu *vcpu)
{
@@ -51,7 +110,7 @@ static const struct vgic_region_attr gic_v5_irs_region = {
.alignment = GICV5_IRS_ALIGN,
};
-static void test_vgic_v5_create(void)
+static void test_vgic_v5_addr_attrs(void)
{
struct kvm_vcpu *vcpu;
struct vm_gic v;
@@ -125,60 +184,92 @@ static void test_vgic_v5_create(void)
vm_gic_destroy(&v);
}
-static void guest_irq_handler(struct ex_regs *regs)
+static void test_vgic_v5_nr_irqs_attrs(void)
{
- bool valid;
- u32 hwirq;
- u64 ia;
- static int count;
-
- /*
- * We have pending interrupts. Should never actually enter WFI
- * here!
- */
- wfi();
- GUEST_SYNC(GUEST_CMD_IS_AWAKE);
-
- ia = gicr_insn(CDIA);
- valid = GICV5_GICR_CDIA_VALID(ia);
-
- GUEST_SYNC(GUEST_CMD_IRQ_CDIA);
-
- if (!valid)
- return;
-
- gsb_ack();
- isb();
-
- hwirq = FIELD_GET(GICV5_GICR_CDIA_INTID, ia);
-
- gic_insn(hwirq, CDDI);
- gic_insn(0, CDEOI);
+ const u32 max_nr_spis = BIT(10);
+ struct kvm_vcpu *vcpu;
+ struct vm_gic v;
+ u32 nr_irqs;
+ int ret;
- GUEST_SYNC(GUEST_CMD_IRQ_DIEOI);
+ v.gic_dev_type = KVM_DEV_TYPE_ARM_VGIC_V5;
+ v.vm = __vm_create(VM_SHAPE_DEFAULT, NR_VCPUS, 0);
+ v.gic_fd = kvm_create_device(v.vm, v.gic_dev_type);
- if (++count >= 2)
- GUEST_DONE();
+ /* Check existing group/attribute */
+ kvm_has_device_attr(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0);
+
+ /* Before userspace sets NR_IRQS, no SPI count has been selected. */
+ nr_irqs = 0xbad;
+ ret = __kvm_device_attr_get(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(!ret && nr_irqs == 0, "GICv5 NR_IRQS defaults to 0 before init");
+
+ /* Too few SPIs */
+ nr_irqs = VGIC_V5_DEFAULT_NR_SPIS - 1;
+ ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(ret && errno == EINVAL, "GICv5 NR_IRQS below minimum");
+
+ /* Not a multiple of 32 */
+ nr_irqs = VGIC_V5_DEFAULT_NR_SPIS + 1;
+ ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(ret && errno == EINVAL, "GICv5 NR_IRQS not 32-aligned");
+
+ /* Larger than KVM's supported VGICv5 SPI count */
+ nr_irqs = max_nr_spis + 32;
+ ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(ret && errno == EINVAL, "GICv5 NR_IRQS above maximum");
+
+ /* Valid custom SPI count */
+ nr_irqs = max_nr_spis;
+ ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(!ret, "GICv5 NR_IRQS accepts valid custom SPI count");
+
+ nr_irqs = 0xbad;
+ ret = __kvm_device_attr_get(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(!ret && nr_irqs == max_nr_spis,
+ "GICv5 NR_IRQS returns SPI count only");
+
+ /* A second successful configuration attempt must be rejected. */
+ nr_irqs = VGIC_V5_DEFAULT_NR_SPIS;
+ ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(ret && errno == EBUSY, "GICv5 NR_IRQS set twice");
+
+ /* The maximum supported count must also initialize successfully. */
+ vcpu = vm_vcpu_add(v.vm, 0, NULL);
+ TEST_ASSERT(vcpu, "Failed to create vCPU");
+ kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL);
- /* Ask for the next interrupt to be injected */
- GUEST_SYNC(GUEST_CMD_IS_READY);
-}
+ vm_gic_destroy(&v);
-static void guest_code(void)
-{
- local_irq_disable();
+ /* If userspace does not set NR_IRQS, init selects the default. */
+ v.vm = __vm_create(VM_SHAPE_DEFAULT, NR_VCPUS, 0);
+ v.gic_fd = kvm_create_device(v.vm, v.gic_dev_type);
+ vcpu = vm_vcpu_add(v.vm, 0, NULL);
+ TEST_ASSERT(vcpu, "Failed to create vCPU");
+ kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL);
- gicv5_cpu_enable_interrupts();
- local_irq_enable();
+ nr_irqs = 0xbad;
+ ret = __kvm_device_attr_get(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(!ret && nr_irqs == VGIC_V5_DEFAULT_NR_SPIS,
+ "GICv5 NR_IRQS defaults to 32 SPIs after init");
- /* Enable the SW_PPI (3) */
- write_sysreg_s(BIT_ULL(3), SYS_ICC_PPI_ENABLER0_EL1);
+ nr_irqs = VGIC_V5_DEFAULT_NR_SPIS * 2;
+ ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, &nr_irqs);
+ TEST_ASSERT(ret && errno == EBUSY, "GICv5 NR_IRQS set after init");
- /* Ask for the first interrupt to be injected */
- GUEST_SYNC(GUEST_CMD_IS_READY);
+ vm_gic_destroy(&v);
- /* Loop forever waiting for interrupts */
- while (1);
}
static void test_vgic_v5_ppis(u32 gic_dev_type)
@@ -294,8 +385,11 @@ int test_kvm_device(u32 gic_dev_type)
void run_tests(u32 gic_dev_type)
{
- pr_info("Test VGICv5 Creation & Setup\n");
- test_vgic_v5_create();
+ pr_info("Test VGICv5 address attrs\n");
+ test_vgic_v5_addr_attrs();
+
+ pr_info("Test VGICv5 NR_IRQS attrs\n");
+ test_vgic_v5_nr_irqs_attrs();
pr_info("Test VGICv5 PPIs\n");
test_vgic_v5_ppis(gic_dev_type);
--
2.34.1
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