[PATCH] clk: rockchip: rk3576: fix source muxes for SPI0..SPI4

[Heiko Stuebner]

On Wed, 05 Aug 2026 17:45:09 +0400, Alexey Charkov wrote:
> The TRM defines available source muxes for SPI0..SPI4 as
>  - b00: clk_gpll_div6_src
>  - b01: clk_gpll_div8_src
>  - b10: clk_cpll_div10_src
>  - b11: clk_xin_osc0_func
> 
> Which doesn't match what the current clock driver implements, making it
> impossible to derive some SPI clock rates such as 37.125 MHz (which
> requires clk_gpll_div8_src as the source mux).
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
      commit: 586ff159ec02533c17dd928641529cb0b52e9c62

Best regards,
-- 
Heiko Stuebner <heiko at sntech.de>