[PATCH v3 6/6] arm64: dts: renesas: r8a78000: Add MDLC nodes
Geert Uytterhoeven
geert+renesas at glider.be
Wed Aug 5 08:20:54 PDT 2026
Add device nodes for the Module Control (MDLC) blocks on the R-Car X5H
(R8A78000) SoC.
Complete hardware desciption of all (H)SCIF serial ports, by linking
them to an MDLC for power domains and resets.
Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
v3:
- Add Reviewed-by,
- Sort MDLC nodes (alphabetically, by label),
v2:
- Split in separate CPG and MDLC patches.
---
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 241 ++++++++++++++++++++++
1 file changed, 241 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 1fe078c7822c01a5..9a07753b221541ed 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/renesas,r8a78000-cpg.h>
+#include <dt-bindings/power/renesas,r8a78000-mdlc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -870,6 +871,8 @@ scif0: serial at c0700000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x40>;
+ resets = <&mdlc_perw 0x40>;
status = "disabled";
};
@@ -882,6 +885,8 @@ scif1: serial at c0704000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x41>;
+ resets = <&mdlc_perw 0x41>;
status = "disabled";
};
@@ -894,6 +899,8 @@ scif3: serial at c0708000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x42>;
+ resets = <&mdlc_perw 0x42>;
status = "disabled";
};
@@ -906,6 +913,8 @@ scif4: serial at c070c000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x43>;
+ resets = <&mdlc_perw 0x43>;
status = "disabled";
};
@@ -918,6 +927,8 @@ hscif0: serial at c0710000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x54>;
+ resets = <&mdlc_perw 0x54>;
status = "disabled";
};
@@ -930,6 +941,8 @@ hscif1: serial at c0714000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x55>;
+ resets = <&mdlc_perw 0x55>;
status = "disabled";
};
@@ -942,6 +955,8 @@ hscif2: serial at c0718000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x56>;
+ resets = <&mdlc_perw 0x56>;
status = "disabled";
};
@@ -954,6 +969,8 @@ hscif3: serial at c071c000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x57>;
+ resets = <&mdlc_perw 0x57>;
status = "disabled";
};
@@ -974,6 +991,230 @@ cpg: clock-controller at c1320000 {
#clock-cells = <1>;
bootph-all;
};
+
+ mdlc_aon: system-controller at c1338000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1338000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_cmnn: system-controller at ca410000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xca410000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_cmns: system-controller at ca510000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xca510000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr0: system-controller at e8000000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8000000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr1: system-controller at e8080000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8080000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr2: system-controller at e8100000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8100000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr3: system-controller at e8180000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8180000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr4: system-controller at e8200000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8200000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr5: system-controller at e8280000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8280000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr6: system-controller at e8300000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8300000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr7: system-controller at e8380000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8380000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_dsp: system-controller at cbe90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xcbe90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_gpc: system-controller at cb510000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xcb510000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_hscn: system-controller at c9c90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc9c90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_hscs: system-controller at de200000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xde200000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_imn: system-controller at c1990000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1990000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ims: system-controller at c1d90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1d90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_mm: system-controller at e9980000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe9980000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_npu0: system-controller at d2c30000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xd2c30000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_npu1: system-controller at d6c30000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xd6c30000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_pere: system-controller at c08f0000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc08f0000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_perw: system-controller at c05d0000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc05d0000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_rt: system-controller at 19440000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0x19440000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_scp: system-controller at c1330000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1330000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_top: system-controller at c6480000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc6480000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vio: system-controller at c5000000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc5000000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vipn: system-controller at c3060000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc3060000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vips: system-controller at c3460000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc3460000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
};
timer {
--
2.43.0
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