[PATCH v8 02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions
Atish Patra
atish.patra at linux.dev
Wed Aug 5 00:30:31 PDT 2026
On 8/4/26 4:35 PM, Paul Walmsley wrote:
> On Wed, 1 Jul 2026, Atish Patra wrote:
>
>> From: Kaiwen Xue <kaiwenx at rivosinc.com>
>>
>> This adds definitions of new CSRs and bits defined in Sxcsrind ISA
>> extension. These CSR enables indirect accesses mechanism to access
>> any CSRs in M-, S-, and VS-mode. The range of the select values
>> and ireg will be define by the ISA extension using Sxcsrind extension.
>>
>> Signed-off-by: Kaiwen Xue <kaiwenx at rivosinc.com>
>> Reviewed-by: Clément Léger <cleger at rivosinc.com>
>> Signed-off-by: Atish Patra <atishp at rivosinc.com>
>
> Thanks. It's easier for folks to grep and cross-reference if the official
> RISC-V extension names are used whenever possible, rather than something
> like Sxcsrind. Queued the following patch for v7.3.
>
Agreed. Thanks!
>
> - Paul
>
>
> RISC-V: Add Smcsrind and Sscrind ISA extension CSR definitions
>
> From: Kaiwen Xue <kaiwenx at rivosinc.com>
>
> This adds definitions of new CSRs and bits defined in the Smcsrind and
> Sscrinq ISA extensions. These CSRs enable the indirect CSR accesses
> mechanism to access any indirect CSRs in M-, S-, and VS-mode. The
> range of the select values and ireg will be defined by the ISA
> extension that are based on the Smcsrind and Sscsrind extensions.
>
> Signed-off-by: Kaiwen Xue <kaiwenx at rivosinc.com>
> Reviewed-by: Clément Léger <cleger at rivosinc.com>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> Reviewed-by: Charlie Jenkins <thecharlesjenkins at gmail.com>
> Tested-by: Charlie Jenkins <thecharlesjenkins at gmail.com>
> Link: https://patch.msgid.link/20260701-counter_delegation-v8-2-7909f863a645@meta.com
> [pjw at kernel.org: clean up the patch description; use official RISC-V extension names]
> Signed-off-by: Paul Walmsley <pjw at kernel.org>
> ---
> arch/riscv/include/asm/csr.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 31b8988f4488..7f09e54a0f9a 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -347,6 +347,12 @@
> /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
> #define CSR_SISELECT 0x150
> #define CSR_SIREG 0x151
> +/* Supervisor-Level Window to Indirectly Accessed Registers (Sscsrind) */
> +#define CSR_SIREG2 0x152
> +#define CSR_SIREG3 0x153
> +#define CSR_SIREG4 0x155
> +#define CSR_SIREG5 0x156
> +#define CSR_SIREG6 0x157
>
> /* Supervisor-Level Interrupts (AIA) */
> #define CSR_STOPEI 0x15c
> @@ -394,6 +400,14 @@
> /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
> #define CSR_VSISELECT 0x250
> #define CSR_VSIREG 0x251
> +/*
> + * VS-Level Window to Indirectly Accessed Registers (H-extension with Sscsrind)
> + */
> +#define CSR_VSIREG2 0x252
> +#define CSR_VSIREG3 0x253
> +#define CSR_VSIREG4 0x255
> +#define CSR_VSIREG5 0x256
> +#define CSR_VSIREG6 0x257
>
> /* VS-Level Interrupts (H-extension with AIA) */
> #define CSR_VSTOPEI 0x25c
> @@ -436,6 +450,12 @@
> /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
> #define CSR_MISELECT 0x350
> #define CSR_MIREG 0x351
> +/* Machine-Level Window to Indirectly Accessed Registers (Smcsrind) */
> +#define CSR_MIREG2 0x352
> +#define CSR_MIREG3 0x353
> +#define CSR_MIREG4 0x355
> +#define CSR_MIREG5 0x356
> +#define CSR_MIREG6 0x357
>
> /* Machine-Level Interrupts (AIA) */
> #define CSR_MTOPEI 0x35c
> @@ -498,6 +518,11 @@
> # define CSR_IEH CSR_MIEH
> # define CSR_ISELECT CSR_MISELECT
> # define CSR_IREG CSR_MIREG
> +# define CSR_IREG2 CSR_MIREG2
> +# define CSR_IREG3 CSR_MIREG3
> +# define CSR_IREG4 CSR_MIREG4
> +# define CSR_IREG5 CSR_MIREG5
> +# define CSR_IREG6 CSR_MIREG6
> # define CSR_IPH CSR_MIPH
> # define CSR_TOPEI CSR_MTOPEI
> # define CSR_TOPI CSR_MTOPI
> @@ -523,6 +548,11 @@
> # define CSR_IEH CSR_SIEH
> # define CSR_ISELECT CSR_SISELECT
> # define CSR_IREG CSR_SIREG
> +# define CSR_IREG2 CSR_SIREG2
> +# define CSR_IREG3 CSR_SIREG3
> +# define CSR_IREG4 CSR_SIREG4
> +# define CSR_IREG5 CSR_SIREG5
> +# define CSR_IREG6 CSR_SIREG6
> # define CSR_IPH CSR_SIPH
> # define CSR_TOPEI CSR_STOPEI
> # define CSR_TOPI CSR_STOPI
>
>
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