[PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus

[Matt Ochs]

> On Apr 29, 2026, at 16:56, Besar Wicaksono <bwicaksono at nvidia.com> wrote:
> 
> PMCCNTR_EL0 may continue to increment on NVIDIA Olympus CPUs while the
> PE is in WFI/WFE. That does not necessarily match the CPU_CYCLES event
> counted by a programmable counter, so using PMCCNTR_EL0 for cycles can
> give results that differ from the programmable counter path.
> 
> Extend the existing PMCCNTR avoidance decision from the SMT case to
> also cover Olympus. Store the result in the common arm_pmu state at
> registration time, so arm_pmuv3 can keep using a single flag when
> deciding whether CPU_CYCLES may use PMCCNTR_EL0.
> 
> Use the cached MIDR from cpu_data to identify Olympus parts and avoid
> reading MIDR_EL1 in the event path.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono at nvidia.com>

Verified on NVIDIA Vera (Olympus CPUs) with UEFI SMT disabled. Confirmed
that grouped cpu_cycles events show ~1x ratio (both on programmable
counters) with the patch vs ~15x inflation without it.

Tested-by: Matthew R. Ochs <mochs at nvidia.com>