[PATCH 2/8] KVM: arm64: Synchronise HCR_EL2 writes on the guest exit path

[Will Deacon]

On Tue, Apr 28, 2026 at 11:30:02AM +0100, Fuad Tabba wrote:
> MSR HCR_EL2 is not self-synchronising. Per ARM DDI 0487 M.b K1.2.4
> (p.K1-16823) and B2.6.1 (p.B2-297), a Context Synchronisation Event
> is required between an HCR_EL2 write and any subsequent direct
> register access at the same EL that depends on the new value being
> in effect.
> 
> On the entry path, the HCR_EL2 write in __activate_traps is followed
> by further EL2 sysreg work (MDCR_EL2, CPTR_EL2, VBAR_EL2, and on the
> speculative-AT errata path SCTLR_EL1/TCR_EL1) before ERET into the
> guest. None of those intervening accesses depend on the new HCR_EL2
> value, and ERET is a CSE per ARM DDI 0487 M.b D1.4.4.1 rule RBWCFK
> (p. D1-7209) conditional on SCTLR_EL2.EOS=1, which is set
> unconditionally by INIT_SCTLR_EL2_MMU_ON (see the prerequisite patch
> in this series). The requirement is therefore satisfied implicitly
> on the activate path.
> 
> The deactivate path is different: after write_sysreg_hcr() in
> __deactivate_traps() further EL2 sysreg work runs before any natural
> CSE - on nVHE, __deactivate_cptr_traps and the VBAR_EL2 write; on
> VHE, the timer context save which reads CNTP_CVAL_EL0 under the new
> TGE/E2H, and the EL1 sysreg restore. Add an explicit isb() at each
> of the two deactivate sites.
> 
> The practical impact today is bounded: HCR_EL2.E2H does not toggle
> in either path, and the trap bits being changed primarily affect
> EL1&0 behaviour. But the architectural rule should be honoured.
> Note that write_sysreg_hcr() itself already issues isb() on the
> Ampere errata path (sysreg.h), confirming the architectural
> expectation; the fast path optimises that away.
> 
> The fix is at the call sites rather than inside write_sysreg_hcr()
> because the macro has many users (e.g. the activate path, at.c,
> hardirq.h, ptrauth alternatives) where the immediately-following
> code either reaches ERET or has another CSE; making the macro emit
> an unconditional ISB would impose unnecessary cost on those
> well-formed users.
> 
> Fixes: 9404673293b0 ("KVM: arm64: timers: Correctly handle TGE flip with CNTPOFF_EL2")
> Signed-off-by: Fuad Tabba <tabba at google.com>
> ---
>  arch/arm64/kvm/hyp/nvhe/switch.c | 11 +++++++++++
>  arch/arm64/kvm/hyp/vhe/switch.c  | 11 +++++++++++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
> index 8d1df3d33595..9d7ead5a5503 100644
> --- a/arch/arm64/kvm/hyp/nvhe/switch.c
> +++ b/arch/arm64/kvm/hyp/nvhe/switch.c
> @@ -105,6 +105,17 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu)
>  	__deactivate_traps_common(vcpu);
>  
>  	write_sysreg_hcr(this_cpu_ptr(&kvm_init_params)->hcr_el2);
> +	/*
> +	 * MSR HCR_EL2 is not self-synchronising. Per ARM ARM K1.2.4 p.K1-16823
> +	 * and B2.6.1 p.B2-297, a Context Synchronisation Event is required
> +	 * between an HCR_EL2 write and any subsequent direct register access at
> +	 * the same EL that depends on the new value being in effect.
> +	 * The activate_traps path falls through to ERET (a CSE), but the
> +	 * deactivate path still executes further EL2 sysreg work (CPTR/VBAR
> +	 * writes below) before any natural CSE, so make the synchronisation
> +	 * explicit.
> +	 */
> +	isb();

Sorry, but I don't understand this. Please can you explain why you think
that CPTR and VBAR have an ordering dependency on HCR_EL2? Preferably,
the comment would talk about the specific fields that are relevant.

Will