[PATCH v2 4/5] coresight: etm3x: introduce struct etm_caps
Jie Gan
jie.gan at oss.qualcomm.com
Sun Apr 12 07:21:54 PDT 2026
On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
> Introduce struct etm_caps to describe ETMv3 capabilities
> and move capabilities information into it.
>
> Since drvdata->etmccr and drvdata->etmccer are used to check
> whether it supports fifofull logic and timestamping,
> remove etmccr and etmccer field from drvdata and add relevant fields
> in etm_caps structure.
>
> Signed-off-by: Yeoreum Yun <yeoreum.yun at arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm.h | 40 +++++++++++--------
> .../coresight/coresight-etm3x-core.c | 33 ++++++++-------
> .../coresight/coresight-etm3x-sysfs.c | 14 ++++---
> 3 files changed, 52 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
> index 1d753cca2943..6fda26039db8 100644
> --- a/drivers/hwtracing/coresight/coresight-etm.h
> +++ b/drivers/hwtracing/coresight/coresight-etm.h
> @@ -140,6 +140,28 @@
> ETM_ADD_COMP_0 | \
> ETM_EVENT_NOT_A)
>
> +/**
> + * struct etmv4_caps - specifics ETM capabilities
> + * @port_size: port size as reported by ETMCR bit 4-6 and 21.
> + * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
> + * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
> + * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
> + * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
> + * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
> + * @fifofull: FIFOFULL logic is present.
> + * @timestamp: Timestamping is implemented.
> + */
> +struct etm_caps {
> + int port_size;
> + u8 nr_addr_cmp;
> + u8 nr_cntr;
> + u8 nr_ext_inp;
> + u8 nr_ext_out;
> + u8 nr_ctxid_cmp;
> + bool fifofull : 1;
> + bool timestamp : 1;
> +};
> +
> /**
> * struct etm_config - configuration information related to an ETM
> * @mode: controls various modes supported by this ETM/PTM.
> @@ -212,19 +234,12 @@ struct etm_config {
> * @csdev: component vitals needed by the framework.
> * @spinlock: only one at a time pls.
> * @cpu: the cpu this component is affined to.
> - * @port_size: port size as reported by ETMCR bit 4-6 and 21.
> * @arch: ETM/PTM version number.
> + * @caps: ETM capabilities.
> * @use_cpu14: true if management registers need to be accessed via CP14.
> * @sticky_enable: true if ETM base configuration has been done.
> * @boot_enable:true if we should start tracing at boot time.
> * @os_unlock: true if access to management registers is allowed.
> - * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
> - * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
> - * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
> - * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
> - * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
> - * @etmccr: value of register ETMCCR.
> - * @etmccer: value of register ETMCCER.
> * @traceid: value of the current ID for this component.
> * @config: structure holding configuration parameters.
> */
> @@ -234,19 +249,12 @@ struct etm_drvdata {
> struct coresight_device *csdev;
> spinlock_t spinlock;
> int cpu;
> - int port_size;
> u8 arch;
> + struct etm_caps caps;
> bool use_cp14;
> bool sticky_enable;
> bool boot_enable;
> bool os_unlock;
> - u8 nr_addr_cmp;
> - u8 nr_cntr;
> - u8 nr_ext_inp;
> - u8 nr_ext_out;
> - u8 nr_ctxid_cmp;
> - u32 etmccr;
> - u32 etmccer;
> u32 traceid;
> struct etm_config config;
> };
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> index a547a6d2e0bd..b7e977defb1c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> {
> int i, rc;
> u32 etmcr;
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
>
> @@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etmcr = etm_readl(drvdata, ETMCR);
> /* Clear setting from a previous run if need be */
> etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
> - etmcr |= drvdata->port_size;
> + etmcr |= caps->port_size;
> etmcr |= ETMCR_ETM_EN;
> etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
> etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
> @@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etm_writel(drvdata, config->enable_event, ETMTEEVR);
> etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
> etm_writel(drvdata, config->fifofull_level, ETMFFLR);
> - for (i = 0; i < drvdata->nr_addr_cmp; i++) {
> + for (i = 0; i < caps->nr_addr_cmp; i++) {
> etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
> etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
> }
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
> etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
> etm_writel(drvdata, config->cntr_rld_event[i],
> @@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
> etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
> etm_writel(drvdata, config->seq_curr_state, ETMSQR);
> - for (i = 0; i < drvdata->nr_ext_out; i++)
> + for (i = 0; i < caps->nr_ext_out; i++)
> etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
> - for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
> + for (i = 0; i < caps->nr_ctxid_cmp; i++)
> etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
> etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
> etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
> @@ -572,7 +573,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata)
> /* Read back sequencer and counters for post trace analysis */
> config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
>
> - for (i = 0; i < drvdata->nr_cntr; i++)
> + for (i = 0; i < caps->nr_cntr; i++)
caps undeclared.
Thanks,
Jie
> config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
>
> etm_set_pwrdwn(drvdata);
> @@ -754,7 +755,9 @@ static void etm_init_arch_data(void *info)
> {
> u32 etmidr;
> u32 etmccr;
> + u32 etmccer;
> struct etm_drvdata *drvdata = info;
> + struct etm_caps *caps = &drvdata->caps;
>
> /* Make sure all registers are accessible */
> etm_os_unlock(drvdata);
> @@ -779,16 +782,18 @@ static void etm_init_arch_data(void *info)
> /* Find all capabilities */
> etmidr = etm_readl(drvdata, ETMIDR);
> drvdata->arch = BMVAL(etmidr, 4, 11);
> - drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
> + caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
> +
> + etmccer = etm_readl(drvdata, ETMCCER);
> + caps->timestamp = !!(drvdata->etmccer & ETMCCER_TIMESTAMP);
caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP);
>
> - drvdata->etmccer = etm_readl(drvdata, ETMCCER);
> etmccr = etm_readl(drvdata, ETMCCR);
> - drvdata->etmccr = etmccr;
> - drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
> - drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
> - drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
> - drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
> - drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
> + caps->fifofull = !!(drvdata->etmccr & ETMCCR_FIFOFULL);
caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL);
> + caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
> + caps->nr_cntr = BMVAL(etmccr, 13, 15);
> + caps->nr_ext_inp = BMVAL(etmccr, 17, 19);
> + caps->nr_ext_out = BMVAL(etmccr, 20, 22);
> + caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
>
> coresight_clear_self_claim_tag_unlocked(&drvdata->csa);
> etm_set_pwrdwn(drvdata);
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> index 762109307b86..0d8dac29d055 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> @@ -111,6 +111,7 @@ static ssize_t mode_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> @@ -131,7 +132,7 @@ static ssize_t mode_store(struct device *dev,
> config->ctrl &= ~ETMCR_CYC_ACC;
>
> if (config->mode & ETM_MODE_STALL) {
> - if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
> + if (!caps->fifofull) {
> dev_warn(dev, "stall mode not supported\n");
> ret = -EINVAL;
> goto err_unlock;
> @@ -141,7 +142,7 @@ static ssize_t mode_store(struct device *dev,
> config->ctrl &= ~ETMCR_STALL_MODE;
>
> if (config->mode & ETM_MODE_TIMESTAMP) {
> - if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
> + if (!caps->timestamp) {
> dev_warn(dev, "timestamp not supported\n");
> ret = -EINVAL;
> goto err_unlock;
> @@ -286,13 +287,14 @@ static ssize_t addr_idx_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> if (ret)
> return ret;
>
> - if (val >= drvdata->nr_addr_cmp)
> + if (val >= caps->nr_addr_cmp)
> return -EINVAL;
>
> /*
> @@ -589,13 +591,14 @@ static ssize_t cntr_idx_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> if (ret)
> return ret;
>
> - if (val >= drvdata->nr_cntr)
> + if (val >= caps->nr_cntr)
> return -EINVAL;
> /*
> * Use spinlock to ensure index doesn't change while it gets
> @@ -999,13 +1002,14 @@ static ssize_t ctxid_idx_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> if (ret)
> return ret;
>
> - if (val >= drvdata->nr_ctxid_cmp)
> + if (val >= caps->nr_ctxid_cmp)
> return -EINVAL;
>
> /*
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