[PATCH v9 05/11] drm/fourcc: Add DRM_FORMAT_X403

[Tomi Valkeinen]

On 10/04/2026 09:07, Tomi Valkeinen wrote:
> Hi,
> 
> On 26/03/2026 16:43, Simon Ser wrote:
>> On Wednesday, March 25th, 2026 at 15:02, Tomi Valkeinen 
>> <tomi.valkeinen at ideasonboard.com> wrote:
>>
>>> +/*
>>> + * 3 plane non-subsampled (444) YCbCr
>>> + * 10 bpc, 30 bits per sample image data in a single contiguous buffer.
>>> + * index 0: Y plane,  [31:0] x:Y2:Y1:Y0    [2:10:10:10] little endian
>>> + * index 1: Cb plane, [31:0] x:Cb2:Cb1:Cb0 [2:10:10:10] little endian
>>> + * index 2: Cr plane, [31:0] x:Cr2:Cr1:Cr0 [2:10:10:10] little endian
>>> + */
>>> +#define DRM_FORMAT_X403        fourcc_code('X', '4', '0', '3')
>>
>> So, this one is different from the Q family, because Q has padding in
> 
> Any idea where the letters (P, Q, S) come from?
> 
>> LSB rather than MSB. Speaking of, maybe we should add "LSB aligned" to
>> the doc comment to make that clear?
> 
> Yes, I can add that.
> 
>> Re-reading the sibling thread about DRM_FORMAT_XV20, sounds like the
>> first digit matches my expectations for sub-sampling. How did you pick
> 
> I just used the name in Xilinx's BSP kernel.
> 
>> the last two digits? I think I would've expected "30" here rather than
>> "03", since the last two planes are Cb Cr rather than Cr Cb.
> 
> Hmm, but X403 is Cb:Cr, and P030 is Cr:Cb, so doesn't 03 make sense 
> here? Oh, but Q401 is Cr:Cb, and it's 01...
> 
> Now that I look at this... I think I have to go back and do more 
> testing. From the Xilinx docs, it looks to me that the XV15/XV20 should 
> have the same CrCb order than X403. But the comments in these patches 
> say otherwise. I'm pretty sure my tests conformed to the comments here, 
> but now I don't feel so sure anymore. It's been more than a year since I 
> wrote the tests and properly tested these, so I have to spend a bit time 
> to get everything up again.

I think the comments are correct. I guess it depends on which way you 
look at this: for P030 etc, starting from the lowest bit, the order is 
Cb:Cr. For X403, starting from the lowest plane, the order is Cb:Cr. And 
that's probably how Xilinx HW "sees" it and thus they use the same Cb:Cr 
order.

But in the comments we describe P030's components starting from the 
highest bit, and thus it's Cr:Cb.

>> Has the first "X" letter been picked arbitrarily? It's already used to
>> denote padding in other formats so I wonder if we should pick that
>> instead of, say, "T".
> I didn't invent the name, I just took the naming Xilinx used. I don't 
> know the history behind it. I assume the "X" is for Xilinx, but I could 
> be wrong here. What would "T" be for? "Tomi"? =)
So... While the Cb:Cr order can be seen both ways, perhaps the Q formats 
are a good reference here to follow, and thus it should be "430", not 
"403", as you suggest. As for the letter... Anything that's not 
currently in use is fine for me =).

  Tomi