[PATCH v3 04/31] coresight: etm4x: Correct polling IDLE bit

[Mike Leach]

On Mon, 15 Sept 2025 at 11:33, Leo Yan <leo.yan at arm.com> wrote:
>
> Since commit 4ff6039ffb79 ("coresight-etm4x: add isb() before reading
> the TRCSTATR"), the code has incorrectly been polling the PMSTABLE bit
> instead of the IDLE bit.
>
> This commit corrects the typo.
>
> Fixes: 4ff6039ffb79 ("coresight-etm4x: add isb() before reading the TRCSTATR")
> Reviewed-by: Yeoreum Yun <yeoreum.yun at arm.com>
> Signed-off-by: Leo Yan <leo.yan at arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 02ad41da7356547a67c53ff0a9146aec844f89da..382ec1a1cdd035e76d451d0112afd3f029ecbdb6 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1926,7 +1926,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
>                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
>
>         /* wait for TRCSTATR.IDLE to go up */
> -       if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
> +       if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) {
>                 dev_err(etm_dev,
>                         "timeout while waiting for Idle Trace Status\n");
>                 etm4_os_unlock(drvdata);
>
> --
> 2.34.1
>

Reviewed-by: Mike Leach <mike.leach at linaro.org>

--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK