[PATCH v1 1/4] arm64: dts: freescale: imx93-var-som: Add WiFi and Bluetooth support

[Frank Li]

On Wed, Oct 29, 2025 at 08:28:46PM +0100, Stefano Radaelli wrote:
> Add device tree nodes for the WiFi and Bluetooth module mounted on the
> VAR-SOM-MX93. The module can be based on either the NXP IW612 or IW611
> chipset, depending on the configuration chosen by the customer.
>
> Regardless of the chipset used, WiFi communicates over SDIO and Bluetooth
> over UART.
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21 at gmail.com>
> ---
>  .../boot/dts/freescale/imx93-var-som.dtsi     | 94 ++++++++++++++++++-
>  1 file changed, 93 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
> index a5f09487d803..97198007b545 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
> @@ -12,7 +12,7 @@ /{
>  	model = "Variscite VAR-SOM-MX93 module";
>  	compatible = "variscite,var-som-mx93", "fsl,imx93";
>
> -	mmc_pwrseq: mmc-pwrseq {
> +	usdhc3_pwrseq: mmc-pwrseq {
>  		compatible = "mmc-pwrseq-simple";
>  		post-power-on-delay-ms = <100>;
>  		power-off-delay-us = <10000>;
> @@ -70,6 +70,18 @@ led at 1 {
>  	};
>  };
>
> +/* BT module */
> +&lpuart5 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>;
> +	uart-has-rtscts;
> +	status = "okay";
> +
> +	bluetooth {
> +		compatible = "nxp,88w8987-bt";
> +	};
> +};
> +
>  /* eMMC */
>  &usdhc1 {
>  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> @@ -81,7 +93,27 @@ &usdhc1 {
>  	status = "okay";
>  };
>
> +/* WiFi */
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> +	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
> +	pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
> +	bus-width = <4>;
> +	mmc-pwrseq = <&usdhc3_pwrseq>;
> +	non-removable;
> +	wakeup-source;
> +	status = "okay";
> +};
> +
>  &iomuxc {
> +	pinctrl_bluetooth: bluetoothgrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_MDIO__GPIO4_IO15                         0x51e
> +		>;
> +	};
> +
>  	pinctrl_eqos: eqosgrp {
>  		fsl,pins = <
>  			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e
> @@ -108,6 +140,15 @@ MX93_PAD_UART2_TXD__GPIO1_IO07			0x51e
>  		>;
>  	};
>
> +	pinctrl_lpuart5: lpuart5grp {
> +		fsl,pins = <
> +			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX   0x31e
> +			MX93_PAD_DAP_TDI__LPUART5_RX            0x31e
> +			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B   0x31e
> +			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B  0x31e
> +		>;
> +	};
> +
>  	pinctrl_usdhc1: usdhc1grp {
>  		fsl,pins = <
>  			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
> @@ -123,4 +164,55 @@ MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
>  			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
>  		>;
>  	};
> +
> +	pinctrl_usdhc3: usdhc3grp {
> +		fsl,pins = <
> +			MX93_PAD_SD3_CLK__USDHC3_CLK                    0x1582 /* SDIO_B_CLK */
> +			MX93_PAD_SD3_CMD__USDHC3_CMD                    0x40001382 /* SDIO_B_CMD */
> +			MX93_PAD_SD3_DATA0__USDHC3_DATA0                0x40001382 /* SDIO_B_D0 */
> +			MX93_PAD_SD3_DATA1__USDHC3_DATA1                0x40001382 /* SDIO_B_D1 */
> +			MX93_PAD_SD3_DATA2__USDHC3_DATA2                0x40001382 /* SDIO_B_D2 */
> +			MX93_PAD_SD3_DATA3__USDHC3_DATA3                0x40001382 /* SDIO_B_D3 */
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> +		fsl,pins = <
> +			MX93_PAD_SD3_CLK__USDHC3_CLK                    0x158e /* SDIO_B_CLK */
> +			MX93_PAD_SD3_CMD__USDHC3_CMD                    0x4000138e /* SDIO_B_CMD */
> +			MX93_PAD_SD3_DATA0__USDHC3_DATA0                0x4000138e /* SDIO_B_D0 */
> +			MX93_PAD_SD3_DATA1__USDHC3_DATA1                0x4000138e /* SDIO_B_D1 */
> +			MX93_PAD_SD3_DATA2__USDHC3_DATA2                0x4000138e /* SDIO_B_D2 */
> +			MX93_PAD_SD3_DATA3__USDHC3_DATA3                0x4000138e /* SDIO_B_D3 */
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> +		fsl,pins = <
> +			MX93_PAD_SD3_CLK__USDHC3_CLK                    0x15fe /* SDIO_B_CLK */
> +			MX93_PAD_SD3_CMD__USDHC3_CMD                    0x400013fe /* SDIO_B_CMD */
> +			MX93_PAD_SD3_DATA0__USDHC3_DATA0                0x400013fe /* SDIO_B_D0 */
> +			MX93_PAD_SD3_DATA1__USDHC3_DATA1                0x400013fe /* SDIO_B_D1 */
> +			MX93_PAD_SD3_DATA2__USDHC3_DATA2                0x400013fe /* SDIO_B_D2 */
> +			MX93_PAD_SD3_DATA3__USDHC3_DATA3                0x400013fe /* SDIO_B_D3 */
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
> +		fsl,pins = <
> +			MX93_PAD_SD3_CLK__GPIO3_IO20            0x400
> +			MX93_PAD_SD3_CMD__GPIO3_IO21            0x400
> +			MX93_PAD_SD3_DATA0__GPIO3_IO22          0x400
> +			MX93_PAD_SD3_DATA1__GPIO3_IO23          0x400
> +			MX93_PAD_SD3_DATA2__GPIO3_IO24          0x400
> +			MX93_PAD_SD3_DATA3__GPIO3_IO25          0x400

Can you align these number to one column with usdhc3-200mhzgrp? at least
it should be same at this patch.

Frank
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_wlan: usdhc3-wlangrp {
> +		fsl,pins = <
> +			MX93_PAD_ENET2_MDC__GPIO4_IO14                  0x51e /* WIFI_REG_ON     */
> +			MX93_PAD_SD2_RESET_B__GPIO3_IO07                0x51e /* WIFI_PWR_EN     */
> +		>;
> +	};
>  };
> --
> 2.43.0
>