[PATCH v4 2/2] arm64: dts: rockchip: add DTs for 100ASK DShanPi A1

[Chukun Pan]

Hi,

>From the schematic, DT still has some things wrong:
https://dl.100ask.net/Hardware/MPU/RK3576-DshanPi-A1/DshanPi-A1-RK3576-SCH_V1.1.pdf

Do you want to resend the whole patch or I send some patches fixing them?

> +	vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 {
> +	vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 {
> +	vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 {
> +	vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 {

These ufs and rtc regulators do not actually exist.

> +	vcc_5v0_typec0: regulator-vcc-5v0-typec0 {
> +		regulator-name = "vcc_5v0_typec0";

The name on the schematic is vbus5v0_typec.

> +&gmac1 {
> +	clock_in_out = "output";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&rgmii_phy1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&eth1m0_miim
> +		     &eth1m0_tx_bus2
> +		     &eth1m0_rx_bus2
> +		     &eth1m0_rgmii_clk
> +		     &eth1m0_rgmii_bus
> +		     &ethm0_clk1_25m_out>;

This should be ethm1_clk0_25m_out.
It seems that the 25m clock is not used.

> +&i2c4 {
> +	status = "okay";
> +
> +	es8388: audio-codec at 10 {
> +		compatible = "everest,es8388", "everest,es8328";
> +		reg = <0x10>;

i2cdetect reports that its address is 0x11

> +		clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>;
> +		AVDD-supply = <&vcca_3v3_s0>;
> +		DVDD-supply = <&vcc_3v3_s0>;
> +		HPVDD-supply = <&vcca_3v3_s0>;
> +		PVDD-supply = <&vcc_3v3_s0>;

These are all from VCC3P3 (VCC3V3_S0).

> +		assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>;
> +		assigned-clock-rates = <12288000>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&sai1m0_mclk>;

In fact, this is connected to sai2.
The schematic is quite misleading here:
RK3576 - SAI2_xxx - SAI1_xxx - ES8388

> +		#sound-dai-cells = <0>;
> +	};
> +};

> +&mdio0 {
> +	rgmii_phy0: phy at 1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0x1>;

The phy address configured in the schematic is 0,
which is also the case in practice.

> +		clocks = <&cru REFCLKO25M_GMAC0_OUT>;

This 25m clock is not used.

> +&mdio1 {
> +	rgmii_phy1: phy at 1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0x1>;

The phy address is 0.

> +		clocks = <&cru REFCLKO25M_GMAC1_OUT>;

This 25m clock is not used.

> +	headphone {
> +		hp_det: hp-det {
> +			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;

According to the schematic, this should be GPIO0_A2?

> +		};
> +	};

> +&sdhci {
> +	bus-width = <8>;
> +	full-pwr-cycle-in-suspend;
> +	max-frequency = <200000000>;

max-frequency is already defined in dtsi

> +&sdmmc {
> +	bus-width = <4>;
> +	cap-mmc-highspeed;
> +	cap-sd-highspeed;
> +	disable-wp;
> +	max-frequency = <200000000>;

max-frequency is already defined in dtsi

> +	sd-uhs-sdr104;
> +	vmmc-supply = <&vcc_3v3_s3>;

This comes from VCC3P3 (VCC3V3_S0).