[PATCH v4 05/11] coresight: etm4x: Ensure context synchronization is not ignored

[Suzuki K Poulose]

On 27/10/2025 10:43, Yeoreum Yun wrote:
> Hi Suzuki,
>> On 24/10/2025 17:45, Leo Yan wrote:
>>> As recommended in section 4.3.7 "Synchronization of register updates" of
>>> ARM IHI0064H.b, a self-hosted trace analyzer should always executes an
>>> ISB instruction after programming the trace unit registers.
>>>
>>> An ISB works as a context synchronization event; a DSB is not required.
>>> Removes the redundant barrier in the enabling flow.
>>
>> It is required for MMIO based instances and must be retained.
> 
> I think it seems fine. since the the etm4x device mmio is mapped as
> Device-nGnRE and according to the section Leo mention:
> 
>    Synchronization when using the memory-mapped interface
>    ..
>    When disabling or enabling the trace unit, the trace analyzer must poll TRCSTATR to check the trace unit is either
>    idle or not idle, as described in Use of the trace unit main enable bit on page 4-169:
>      • When the memory is marked as Device-nGnRE or stronger.
>        — Write to enable or disable the trace unit.
>        — Poll TRCSTATR to ensure the previous write has completed.
>        — Execute an ISB operation.
> 
> Therefore, we can omit the dsb in here.

You are right, to be precise, as long as we quote the following, I am fine.


Section 4.3.7, Synchronization when using the memory-mapped interface -

When using the memory-mapped interface to program the trace unit, the 
trace analyzer must ensure that writes have completed, to ensure that 
the trace unit is fully programmed and either enabled or disabled.

• If the memory marked is as Device-nGnRE or stronger, read back the 
value of any register in the trace unit. This relies on peripheral 
coherence order defined in the Arm architecture.


Suzuki


> 
> [...]
> 
> Thanks.
> 
> --
> Sincerely,
> Yeoreum Yun